[HN Gopher] Reticle: Virtual Machine for Programming Modern FPGA...
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       Reticle: Virtual Machine for Programming Modern FPGAs [pdf]
        
       Author : ingve
       Score  : 44 points
       Date   : 2021-05-07 11:32 UTC (1 days ago)
        
 (HTM) web link (homes.cs.washington.edu)
 (TXT) w3m dump (homes.cs.washington.edu)
        
       | marmaduke wrote:
       | Is this a better way to transition from GPU to FPGA than the
       | OpenCL tool chains available for FPGA?
        
       | amelius wrote:
       | Does this avoid the vendor lock-in and proprietary tool
       | nightmare?
        
         | kown7 wrote:
         | For the most part, it looks like it. I don't see how you're
         | being more productive though.
        
         | aseipp wrote:
         | No -- there's no way to avoid the place and route phase for an
         | FPGA, which is responsible for choosing _where_ the components
         | on the device that collectively implement your desired design
         | are placed, and ensures they 're wired together. Performing
         | that task requires detailed knowledge of the silicon, and for
         | high-end FPGAs that only can only be done by the proprietary
         | tools the vendor provides. There are also many other tasks
         | (e.g. timing analysis) that a tool like this wouldn't perform,
         | which would also need the proprietary tools and silicon info
         | anyway.
         | 
         | The goal of this project is to provide a better source language
         | that various HDLs can target their compilers at. Currently,
         | every toolchain _de facto_ targets some subset of Verilog as
         | its output language, and expects another tool (the synthesizer,
         | also often proprietary) to map Verilog constructs directly onto
         | silicon features, like multipliers -- and those multipliers get
         | fed to the place  & route tools. This approach works, but it's
         | generally brittle, because no two Verilog compilers behave
         | exactly the same (among other reasons) so the contortions
         | needed to map constructs reliably tends to require a lot of
         | trial and error and weird rituals.
        
       | NHQ wrote:
       | How much like an FPGA would it be to use DRAM for the lookup
       | tables, and very basic CPU for routing?
        
         | mhh__ wrote:
         | If you are fabricating that inside the FPGA then there is no
         | mythical creature to stop you doing it but the power usage and
         | achievable clock speeds might not be very impressive.
        
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       (page generated 2021-05-08 23:01 UTC)