[HN Gopher] The NEO430 Processor
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       The NEO430 Processor
        
       Author : kqr2
       Score  : 28 points
       Date   : 2021-03-27 06:17 UTC (1 days ago)
        
 (HTM) web link (github.com)
 (TXT) w3m dump (github.com)
        
       | anonymousiam wrote:
       | Interesting idea, but with some drawbacks. 1) No JTAG interface.
       | 2) No SEU mitigations. 3) Power consumption likely at least two
       | orders of magnitude higher. 4) Higher cost.
       | 
       | Some potential benefits: 1) Runs faster. 2) Reduced part count.
       | 3) Easy integration with other FPGA elements.
       | 
       | I will add that the GNU tool chain for the MSP-430 is horrible.
       | TI has a much better C compiler which they previously charged
       | $100 for, but it's been free for the last four years.
        
       | mkesper wrote:
       | TFA: This project is still active but is currently shelved as I
       | am focusing on the NEO430's "big brother": The RISC-V-powered
       | 32-bit NEORV32 https://github.com/stnolting/neorv32.
        
         | elromulous wrote:
         | I was about to post with "how is this different from the
         | various other vhdl / verilog risc v implementations", but saw
         | the incredibly detailed datasheet. That alone is very
         | impressive.
        
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       (page generated 2021-03-28 23:01 UTC)