[HN Gopher] SiPearl Lets Rhea Design Leak: 72x Zeus Cores, 4x HB...
___________________________________________________________________
SiPearl Lets Rhea Design Leak: 72x Zeus Cores, 4x HBM2E, 4-6 DDR5
Author : rbanffy
Score : 57 points
Date : 2021-02-25 09:53 UTC (13 hours ago)
(HTM) web link (www.anandtech.com)
(TXT) w3m dump (www.anandtech.com)
| Pet_Ant wrote:
| >the project uses Arm's upcoming Neoverse "Zeus" cores which
| succeed the Neoverse N1 Ares cores
|
| Would have much rather seen rise-v for true independence. Maybe
| the cores will be swappable?
|
| This does seem like legitimately a good case for it with the
| means to succeed.
| ksec wrote:
| Need (2020) In the Title.
|
| Also not sure what is worthy of discussions or if there are
| anything new.
| Google234 wrote:
| It hasn't been discussed on this site yet so I don't have a
| problem with the post
| fnord77 wrote:
| "leak"
| Zenst wrote:
| Yes, I'm very mindful how companies and politicians have
| accidents like this - so may well be what I class as "tactile
| marketing" If we see some share or funding for that company
| soon, then that would be handy PR then.
|
| [EDIT ADD] Seems they had funding just over a year ago, so be
| due another round soon I'd expect, that with staggered PR press
| releases with a slant of European super computer and with that,
| this leak probably do them more good than harm PR wise - more
| so if they are in position to be seeking new investment, which
| it does look like they will - at least how it feels too me.
| wyldfire wrote:
| > PCIe board
|
| That shows up on the roadmap. Does that mean it's only available
| as an add-in card?
| floatboth wrote:
| > hybrid memory subsystem comprising four HBM2E memory stacks as
| well as four or six regular DDR5 memory channels
|
| YES! That's what I wanted to see happen.. I'm surprised AMD
| wasn't first to do this, considering their history with HBM GPUs.
| dragontamer wrote:
| Hybrid memory systems are famously difficult to work with.
|
| See XBox 360 eDRAM, Xeon Phi (DDR4 + HMC version), among
| others. Its a computer architecture that keeps showing up every
| few years... programmers get frustrated with the split-memory
| architecture. So its rare for such a system to ever become
| popular.
|
| ----------
|
| HBM RAM doesn't have any better latency characteristics than
| DDR4. Traversing a linked-list in HBM will take the same amount
| of time (maybe even a bit longer) than DDR4. As such, its non-
| obvious how to optimize the split-memory operations.
|
| NUMA-style mallocs / frees (malloc to a particular memory
| location) don't really match the performance characteristics
| either. Its not that one or the other RAM has better latency...
| its that one RAM has more BANDWIDTH than the other. NUMA-style
| is already more complicated than most programmers are willing
| to work with, and yet its still not enough to capture the
| performance attributes of HBM vs DDR4.
| ChuckNorris89 wrote:
| AMD was almost sinking till a few years ago, so throwing the
| little money they had in expensive pipe dreams like this would
| have been their end.
|
| Best they stuck to their strengths like Ryzen CPUs and Radeon
| GPUs and turned the ship around.
| rbanffy wrote:
| Processors designed for HPC, GPUs and generic server CPUs
| have different evolutionary forces acting on them. We can be
| sure AMD did at least some simulations on EPYC about how HBM
| memory would impact performance on server workloads.
|
| It all depends on the workload and demand. AMD can have much
| larger volume with a part tailored for the space between HEDT
| and server than with one tailored to HPC workloads.
|
| I would _love_ to misuse one of these as my personal
| workstation (just I would have loved to use a Xeon Phi), but
| not all my purchasing decisions are strictly rational.
| dekken_ wrote:
| > September 8, 2020
| rbanffy wrote:
| I wonder if the link could change to
| https://www.tomshardware.com/news/sipearl-rhea-n6-open-silic...
___________________________________________________________________
(page generated 2021-02-25 23:03 UTC)