https://johnnysswlab.com/memory-subsystem-optimizations/ Johnny's Software Lab Johnny's Software Lab We help you deliver fast software * Home * Performance + 2 Minute Reads + C++ Performance + Standard Library and Performance + Algorithms and Performance + Toolchain and Performance + Help the Compiler + Performance Analysis Tools + Computational Performance + Low Level Performance + Parallelization + Multithreaded Performance + Performance Contest * Debugging * Developer Tools * Vectorization Workshop * Need help? * Talks * Contact * About us Menu Memory Subsystem Optimizations In this blog I wrote 18 blog posts about memory subsystem optimizations. By memory subsystem optimizations, I mean optimizations that aim at making software faster by better using the memory subsystem. Most of them are applicable to software that works with large datasets; but some of them are applicable to software that works with any data regardless of its size. Do you need to discuss a performance problem in your project? Or maybe you want a vectorization training for yourself or your team? Contact us Or follow us on LinkedIn , Twitter or Mastodon and get notified as soon as new content becomes available. Here is a list of all posts that we covered on Johnny's Software Lab: Topic Description Link Decreasing the Number of Memory We speed up software by keeping Accesses 1/2 Decreasing Total data in registers instead of Memory Accesses reloading it from the memory Decreasing the subsystem several times. Number of Memory Accesses: The Compiler's Secret Life 2/2 Changing the Data By changing our data access For Software Access Pattern to pattern we increase the Performance, the Increase Locality possibility our data is in the Way Data is fastest level of data cache. Accessed Matters! Changing the Data Selecting proper class data Software Layout: Classes layout can improve software Performance and performance. Class Layout By changing the data layout of Faster hash maps, Changing the Data common data structures, such as binary trees etc. Layout: Data linked lists, trees or hash through data layout Structures maps we can improve their modification performance. Memory efficiency can be Memory consumption, Decreasing the improved by decreasing the dataset size and Dataset Size dataset size. This results in performance: how speed improvements as well. does it all relate? Whereas data layout is determined at compile time, memory layout is determined by Changing the the system allocator at Performance Through Memory Layout runtime. We examine how Memory Layout changing the memory layout using custom allocators influences software performance. Instruction-level parallelism in practice: speeding Some codes cannot utilize the up memory-bound Increasing memory subsystem fully because programs with low instruction-level of instruction dependencies. ILP parallelism Here we investigate techniques that break dependencies and Hiding Memory improve performance. Latency With In-Order CPU Cores OR How Compilers Optimize Your Code Explicit software prefetches Software tell hardware that you will be The pros and cons prefetching for accessing a certain piece of of explicit random data data soon. When used smartly, software accesses they can improve software prefetching performance. TLB cache is a small cache that speeds up translation of Speeding Up virtual to physical memory Translation of Decreasing TLB addresses. In some cases, it Virtual To Physical cache misses can be the reason for poor Memory Addresses: performance. We investigate TLB and Huge Pages techniques for decreasing TLB cache misses. In some cases, we don't care about software performance, but Saving the memory we do care about being a good Frugal Programming: subsystem neighbor. We investigate Saving Memory bandwidth techniques that make our Subsystem Bandwidth software consume least possible amount of memory subsystem resources. We investigate the delicate Unexpected Ways Branch prediction interplay of the branch Memory Subsystem and data caches prediction and the memory Interacts with subsystem. Branch Prediction Here we investigate how memory Multithreading subsystem behaves in the Multithreading and and the Memory presence of multithreading and the Memory Subsystem how does that effect software Subsystem speed. Latency-Sensitive Applications and In some cases we are more the Memory interested in short latency Subsystem: Keeping than high throughput. We the Data in the Low-latency investigate the techniques Cache applications aimed at improving latency, either by modifying our Latency-Sensitive programs, or reconfiguring the Application and the system. Memory Subsystem Part 2: Memory Management Mechanisms Measuring Memory We talk about tools and metrics Measuring Memory Subsystem you can use to understand what Subsystem Performance is going on with the memory Performance subsystem. A few remaining topics related Memory Subsystem Other topics to memory subsystem Optimizations - The optimizations that didn't fit Remaining Topics any of the other categories. Any feedback on the material covered in this posts will be highly appreciated. Do you need to discuss a performance problem in your project? Or maybe you want a vectorization training for yourself or your team? Contact us Or follow us on LinkedIn , Twitter or Mastodon and get notified as soon as new content becomes available. Leave a Reply Cancel reply Your email address will not be published. Required fields are marked * [ ] [ ] [ ] [ ] [ ] [ ] [ ] Comment *[ ] Name * [ ] Email * [ ] Website [ ] [ ] Save my name, email, and website in this browser for the next time I comment. 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