https://ysyx.oscc.cc/docs/en/ Official documentsv24.07 Study Handouts Course HomeCourse Home * v24.07 * v23.06(The 6th) Study HandoutsStudy Handouts * F Stage + F1 How to Ask Smart Questions + F2 Installing and Using Logisim + F3 The basic of digital and logic circuits + F4 State Machine Model of Computer Systems + F5 Simple Processor Supporting Sequence Summation + F6 A Fully Functional Mini RISC-V Processor * E Stage + E1 C language programming + E2 Hardware Description Language + E3 Linux System Installation and Basic Usage + E4 From C Code to Binary Program + E5 From RTL Code to Tapeout-Ready Layout + E6 Complete PA1 + E7 Submission of pre-study defense application * D Stage + D1 NEMU with RV32IM Support + D2 Machine-level representation of programs + D3 Runtime environment + D4 Implementing a mini RISC-V Processor using RTL + D5 Devices and Input/Output * C Stage + C1 Tools and Infrastructure + C2 RV32E Single Cycle NPC + C3 Debugging Techniques + C4 ELF Files and Linking + C5 Exception Handling and RT-Thread * B Stage + B1 Bus + B2 SoC Computer System + B3 Time Analysis and Optimization + B4 Performance Optimization and Simple Cache + B5 Pipelined Processor PA HandoutsPA Handouts * Nanjing University "Computer System Fundamentals" Experiment (PA) + PA0 - The Eve of World Birth: Development Environment Configuration + PA1 - The Chapter of Creating the Universe: The Simplest Computer + PA2 - Simple and complex machines: von Neumann computer systems + PA3 - A Journey Through Time and Space: Batch Processing System + PA4 - The magic of reality and fiction: Time-sharing multitasking Select LanguagesSelect Languages * Jian Ti Zhong Wen * English Course HomeCourse Home * v24.07 * v23.06(The 6th) Study HandoutsStudy Handouts * F Stage + F1 How to Ask Smart Questions + F2 Installing and Using Logisim + F3 The basic of digital and logic circuits + F4 State Machine Model of Computer Systems + F5 Simple Processor Supporting Sequence Summation + F6 A Fully Functional Mini RISC-V Processor * E Stage + E1 C language programming + E2 Hardware Description Language + E3 Linux System Installation and Basic Usage + E4 From C Code to Binary Program + E5 From RTL Code to Tapeout-Ready Layout + E6 Complete PA1 + E7 Submission of pre-study defense application * D Stage + D1 NEMU with RV32IM Support + D2 Machine-level representation of programs + D3 Runtime environment + D4 Implementing a mini RISC-V Processor using RTL + D5 Devices and Input/Output * C Stage + C1 Tools and Infrastructure + C2 RV32E Single Cycle NPC + C3 Debugging Techniques + C4 ELF Files and Linking + C5 Exception Handling and RT-Thread * B Stage + B1 Bus + B2 SoC Computer System + B3 Time Analysis and Optimization + B4 Performance Optimization and Simple Cache + B5 Pipelined Processor PA HandoutsPA Handouts * Nanjing University "Computer System Fundamentals" Experiment (PA) + PA0 - The Eve of World Birth: Development Environment Configuration + PA1 - The Chapter of Creating the Universe: The Simplest Computer + PA2 - Simple and complex machines: von Neumann computer systems + PA3 - A Journey Through Time and Space: Batch Processing System + PA4 - The magic of reality and fiction: Time-sharing multitasking Select LanguagesSelect Languages * Jian Ti Zhong Wen * English * "One Student One Chip" v24.07 Course Homepage + Learning Resources + Past Courses Homepage + Other Resources + Record of events # "One Student One Chip" v24.07 Course Homepage * Live teaching sessions will start in September 2025. Stay tuned. * If you find errors in the lab handouts or materials, or have questions or suggestions about the experiments, please contact Yu Zihao via email (yuzihao#ict.ac.cn). # Learning Resources * The Time column indicates estimated completion time in hours. + Content marked with an estimated completion time of 2 typically does not include programming assignments, but consists of 2 hours of video lectures designed to supplement related knowledge. + Given varying student proficiency levels, these estimates are based on "intermediate-level" learners. This "intermediate level" does not mean "scoring above 80% in programming courses," but rather "having a positive learning attitude, having written a single program exceeding 500 lines of code, and understanding debugging." + If you are a complete beginner, expect to spend 2-3 times this amount of time to complete the study. Don't be discouraged--as the saying goes, "Some learn earlier, some later." The reason other students progress faster is largely because they've already invested effort to overcome the beginner stage. * Click icons to jump to corresponding resources * Full lecture notes accessible via the top-right navigation bar * Course materials created with reveal.jsopen in new window, exportable to PDF--see this guideopen in new window * S-stage lecture content remains under development C = C language ( programs / emulators / system software ) | R = RISC-V instruction set | P = Processor design | T = Tools Stage Number Task Time Course Slide Video C R P T Handout How to Ask Smart 2 Questions Installing and Using 2 - - Logisim The basic of digital 20 F and logic circuits Stage State Machine Model of 5 Computer Systems Simple Processor Supporting Sequence 5 - - Summation A Fully Functional Mini 5 - - RISC-V Processor C language programming 20 Hardware Description 20 Language Linux System E Installation and Basic 10 Stage Usage From C Code to Binary 10 Program From RTL Code to 20 - - Tapeout-Ready Layout Complete PA1 20 Submission of pre-study defense application NEMU with RV32IM 10 Support Machine-level representation of 2 programs I Machine-level D representation of 2 Stage programs II AM Runtime environment 5 Implementing a mini RISC-V Processor using 5 - - RTL Devices and Input/ 10 Output Tools and 5 Infrastructure C RV32E Single Cycle NPC 5 Stage Debugging Techniques 2 ELF Files and Linking 2 Exception Handling and 15 RT-Thread C Stage Completion Preparation and Assessment Bus 10 SoC Computer System I 15 SoC Computer System II 15 B Time Analysis and 5 - - Stage Optimization Performance Optimization and Simple 20 Cache Pipelined Processor 20 B Stage Tapeout Preparation and Assessment Multiplication and 0 Division Module System Calls and 0 Applications Virtual Memory 0 A Management Stage Privilege Level and xv6 0 Booting Linux and 0 Debian Advanced Cache 0 Advanced Branch 0 Prediction A Stage Tapeout Preparation and Assessment S Under Construction ... 0 Stage Page loading bar is stuck? If the progress bar is stuck for more than 3 seconds when jumping to a new page, it's probably because we pushed a new version of the page. Given that we're still updating and revising the documentation frequently, it may be easier to experience stuck jumps in the near future. In this case, just refresh You can continue to learn! # Past Courses Homepage Accessible via the "Courses Home" link in the top navigation bar. # Other Resources * The RISC-V Reader: An Open Architecture Atlas By David Patterson and Andrew Wathelet * Computer Systems: Based on the RISC-V + Linux Platform Edited by Yuan Chunfeng, Yu Zihao, and Chen Luopen in new window * Digital Design and Computer Architecture - Spring 2023, Onur Mutlu@ETH Zurichopen in new window * Questioning template # Record of events * 2024/07/14 - "One Student One Chip" 2024 Summer Workshopopen in new window * 2023/08/25 - Open Source Chip Technology Ecology Forum (formerly "One Student One Chip" Technology Forum) * 2023/07/02 - 6th "One Student One Chip" Kick-Off Meetingopen in new window * 2022/11/20 - Chip Open Source and Agile Design from a Software Engineering Perspective(Yungang Bao)open in new window * 2022/08/28 - The First "One Student One Chip" Technical Forum and the Fifth Launching Meeting * 2022/03/12 - Hardware-software collaboration capabilities in chip design(Yue Jin, Bohan Hu, Zeyu Gao)open in new window Last Updated: Contributors: myyerrol, Miao Yuyang