https://book.rvemu.app/

 1. Writing a RISC-V Emulator in Rust
 2. 1. Hardware Components
 3.
     1. 1.1. CPU with Two Instructions
     2. 1.2. Memory and System Bus
     3. 1.3. Control and Status Registers
 4. 2. Instruction Set
 5.
     1. 2.1. RV64I Base Integer Instruction Set

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Writing a RISC-V Emulator in Rust

 
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Writing a RISC-V Emulator in Rust

NOTE: This project is actively ongoing. Pages are not perfect yet and
it possible to change dramatically.

Introduction

This is the book for writing a 64-bit RISC-V emulator from scratch in
Rust. You can run xv6, a simple Unix-like OS, in your emulator once
you finish the book.

You'll learn the basic computer architecture such as ISA, previleged
architecture, exceptions, interrupts, peripheral devices, and virtual
memory system from making an emulator.

The source code used in this book is available at d0iasm/
rvemu-for-book.

Chapter 1

Chapter 1 shows all hardward components we need to implement for
running xv6.

 1. CPU with Two Instructions
 2. Memory and System Bus
 3. Control and Status Registers
 4. Privileged Architecture
 5. Exceptions
 6. PLIC (a platform-level interrupt controller) and CLINT (a
    core-local interrupter)
 7. UART (a universal asynchronous receiver-transmitter)
 8. Interrupts
 9. Virtio
10. Virtual Memory System

Chapter 2

Chapter 2 shows all ISAs we need to implement for running xv6.

  * RV64I Base Integer Instruction Set
  * "M" Standard Extension for Integer Multiplication and Division
  * "A" Standard Extension for AtomicInstructions

Outcome

Once you read this book and implement the emulator, you will be able
to run xv6 in your emulator!

Demo for running xv6 on the emulator

Contact

The author is @d0iasm and please feel free to ask and request
anything to me via Twitter or GitHub issues!