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Donate arxiv logo > cs > arXiv:2505.24363 [ ] Help | Advanced Search [All fields ] Search arXiv logo Cornell University Logo [ ] GO quick links * Login * Help Pages * About Computer Science > Hardware Architecture arXiv:2505.24363 (cs) [Submitted on 30 May 2025] Title:Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution Authors:Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi, Nils Wistoff, Cesar Fuguet, Davide Rossi, Luca Benini View a PDF of the paper titled Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution, by Zexin Fu and 6 other authors View PDF HTML (experimental) Abstract:Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support. In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core. We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency. Subjects: Hardware Architecture (cs.AR) Cite as: arXiv:2505.24363 [cs.AR] (or arXiv:2505.24363v1 [cs.AR] for this version) https://doi.org/10.48550/arXiv.2505.24363 Focus to learn more arXiv-issued DOI via DataCite https://doi.org/10.1145/3719276.3725186 Related DOI: Focus to learn more DOI(s) linking to related resources Submission history From: Zexin Fu [view email] [v1] Fri, 30 May 2025 08:54:47 UTC (593 KB) Full-text links: Access Paper: View a PDF of the paper titled Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution, by Zexin Fu and 6 other authors * View PDF * HTML (experimental) * TeX Source * Other Formats license icon view license Current browse context: cs.AR < prev | next > new | recent | 2025-05 Change to browse by: cs References & Citations * NASA ADS * Google Scholar * Semantic Scholar a export BibTeX citation Loading... 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