https://www.techpowerup.com/337950/pci-sig-releases-pcie-7-0-specification-to-support-128-0-gt-s-transfer-rates [_b464a83b] [ ] [ ] * Home * Reviews * Forums * Downloads * Case Mod Gallery * Databases [ ] + Databases... Back + VGA Bios Collection + GPU Database + CPU Database + SSD Database + Review Database + Upcoming Hardware * Our Software [ ] + Our Software... Back + GPU-Z + RealTemp + NVCleanstall + TPUCapture + MemTest64 * More [ ] + More... Back + Articles + Old Stuff + Computer Trivia + TPU Live + RAM Latency Calculator * Contact Us * Wednesday, June 11th 2025 PCI-SIG Releases PCIe 7.0 Specification to Support 128.0 GT/s Transfer Rates Press Release by Nomad76 Today, 14:00 Discuss (12 Comments) PCI-SIG today announced the official release of the PCI Express (PCIe) 7.0 specification, reaching 128.0 GT/s, to members. PCIe 7.0 specification targets data-driven applications like AI/ML, 800G Ethernet, cloud, and Quantum computing. Pathfinding for the PCIe 8.0 specification is already in progress to continue supporting the industry's investments and product roadmaps in the PCIe technology ecosystem. PCIe 7.0 Specification Features * Delivers 128.0 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration * Utilizes PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and Flit-based encoding * Provides improved power efficiency * Maintains backwards compatibility with previous generations of PCIe technology [vO4XmYFeALDG6j2t_thm] [oHjwjsBWoXlyp8HJ_thm] [N8bHBhchaVyXKDpU_thm] "PCIe technology has served as the high-bandwidth, low-latency IO interconnect of choice for over two decades and we are pleased to announce the release of the PCIe 7.0 specification, which continues our long-standing tradition of doubling the IO bandwidth every three years," said Al Yanes, PCI-SIG President and Chairperson. "As artificial intelligence applications continue to scale rapidly, the next generation of PCIe technology meets the bandwidth demands of data-intensive markets deploying AI, including hyperscale data centers, high performance computing (HPC), automotive and military/ aerospace." "It's a special occasion when a PCIe specification hits the final version," observed Ian Cutress, Chief Analyst and CEO, More Than Moore. "The rise in the demand for both compute and networking, enabled through PCIe technology, is at an all-time high, despite the complexities of creating standards in the industry around high-speed signaling. Datacenters are ready to start deploying networks built on PCIe 7.0 technology, and almost every ASIC company I talk to is already engaged with the IP providers and are set to take advantage. Even with the popularity and focus that went into PCIe 6.0 deployment, the PCIe 7.0 specification has more enthusiasm than any previous version." Source: PCI-SIG Related News * Tags: * final * HPC * PCI-SIG * PCIe * PCIe 7.0 * specification * Mar 6th 2025 Bolt Graphics Announces Zeus GPU for High Performance Workloads (19) * Mar 21st 2025 PCI-SIG Ratifies PCI Express 7.0 Specification to Reach 128 GT/s (18) * Jun 11th 2025 Ultra Ethernet Consortium Announces the Release of UEC Specification 1.0 (7) * Jun 11th 2025 Synopsys Achieves PCIe 6.x Interoperability Milestone with Broadcom's PEX90000 Series Switch (0) * Apr 8th 2025 UALink Consortium Releases the Ultra Accelerator Link 200G 1.0 Specification (0) * Jan 22nd 2025 Montage Technology Samples PCIe 6.x / CXL 3.x Retimer Chips (0) * Oct 28th 2024 Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The Future (7) * Aug 6th 2024 NVM Express Releases NVMe 2.1 Specifications (3) * Oct 14th 2024 Credo Announces PCI Express 6/7, Compute Express Link CXL 3.x Retimers, and AEC PCI Express Product Line at OCP Summit 2024 (3) * Oct 9th 2024 Astera Labs Introduces New Portfolio of Fabric Switches Purpose-Built for AI Infrastructure at Cloud-Scale (0) Add your own comment 12 Comments on PCI-SIG Releases PCIe 7.0 Specification to Support 128.0 GT/s Transfer Rates #1 Bobaganoosh [200] (I remembered after posting this gif that you're not supposed to just post a gif or picture as a reply without some kind of comment)...well...cool. I haven't even seen PCIe 6 in the world yet, but now we have 7.0. I guess they have to release the spec before we can use it, but it sometimes seems wild when we're not even utilizing a couple gens ago in the mainstream. Posted on Jun 11th 2025, 14:13 Reply #2 Battler624 Am I wrong or are the numbers exactly twice what they should be? Isn't PCIE 4, at 4 lanes, 8GB/s? Posted on Jun 11th 2025, 14:17 Reply #3 LabRat 891 Meanwhile, PCB designers [200] Posted on Jun 11th 2025, 14:18 Reply #4 TumbleGeorge Battler624Isn't PCIE 4, at 4 lanes, 8GB/s? Yes in one direction. But marketing sum speed in two directions. Posted on Jun 11th 2025, 14:21 Reply #5 PrEzi Wonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ? Posted on Jun 11th 2025, 14:43 Reply #6 umeng2002 Damn, I'm still on 4.0. My wife is going to leave me, and my colleagues at work are going to laugh at me. Posted on Jun 11th 2025, 14:48 Reply #7 Mysteoa umeng2002Damn, I'm still on 4.0. My wife is going to leave me, and my colleagues at work are going to laugh at me. I'm still on 3.0 Posted on Jun 11th 2025, 15:09 Reply #8 Nomad76 News Editor PrEziWonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ? The optical interconnectivity is going to be a must, even with PCIe 6.0, there are already some of the big-names working on possible solutions. We did cover that area in the past with news (just some recent examples below). To summarize, optical (at least on "industrial/enterprise" areas) is a must. For mortals like us, it's not viable. www.techpowerup.com/334714/ marvell-demonstrates-industrys-first-end-to-end-pcie-gen-6-over-optics-at-ofc-2025 www.techpowerup.com/334337/ nvidia-commercializes-silicon-photonics-with-infiniband-and-ethernet-switches www.techpowerup.com/332829/ stmicroelectronics-enhances-optical-interconnects-for-faster-ai-and-cloud-datacenters www.techpowerup.com/334861/ ayar-labs-unveils-worlds-first-ucie-optical-chiplet-for-ai-scale-up-architectures Posted on Jun 11th 2025, 15:14 Reply #9 bonehead123 umeng2002Damn, I'm still on 4.0. My wife is going to leave me, and my colleagues at work are going to laugh at me. Well, my wife said that if I didn't immediately start using pcie-12xxx, she was gonna leave me too.... So I did, & she didn't, so all is good here, hehehehe :D As for my cowerkers, I can just say "F" them, since I work remotely, I don't really give a rat's ass what they say about me around the office, cause I know NONE of them have the balls to say anything to my face, which they only see like once every 45-60 days, and they know I would fire their collective asses in a friggin heartbeat if they did say something stupid to me ! But back on topic.......yeehaw to the pci-e folks, now gimme v12 or gimme death..:roll: Posted on Jun 11th 2025, 15:39 Reply #10 PrEzi Nomad76The optical interconnectivity is going to be a must, even with PCIe 6.0, there are already some of the big-names working on possible solutions. We did cover that area in the past with news (just some recent examples below). To summarize, optical (at least on "industrial/enterprise" areas) is a must. For mortals like us, it's not viable. www.techpowerup.com/334714/ marvell-demonstrates-industrys-first-end-to-end-pcie-gen-6-over-optics-at-ofc-2025 www.techpowerup.com/334337/ nvidia-commercializes-silicon-photonics-with-infiniband-and-ethernet-switches www.techpowerup.com/332829/ stmicroelectronics-enhances-optical-interconnects-for-faster-ai-and-cloud-datacenters www.techpowerup.com/334861/ ayar-labs-unveils-worlds-first-ucie-optical-chiplet-for-ai-scale-up-architectures I am wondering why are you so defensive... In the past few months you have covered some of the optical tech based on the old spec (I assume pre 6.4 ?). True. But no word on how PCI-SIGs Optical Aware Retimer Engineering Change Notice (ECN) amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe (optical) retimer-based solution. Might not be important for consumers.... but we will see.... Maybe fibre on the mainboard would be cheaper for the end consumer too, if too many standard retimers need to be included to warrant a clean signaling across the mainboard. Posted on Jun 11th 2025, 15:39 Reply #11 Nomad76 News Editor PrEziI am wondering why are you so defensive... In the past few months you have covered some of the optical tech based on the old spec (I assume pre 6.4 ?). True. But no word on how PCI-SIGs Optical Aware Retimer Engineering Change Notice (ECN) amends the PCIe 6.4 specification and the new PCIe 7.0 specification to include a PCIe (optical) retimer-based solution. Might not be important for consumers.... but we will see.... Maybe fibre on the mainboard would be cheaper for the end consumer too, if too many standard retimers need to be included to warrant a clean signaling across the mainboard. Not being defensive at all :) "The PCI-SIG Optical Work Group is exploring an optical interconnect supporting a wide range of optical technologies to make PCIe architecture more optical friendly. Additional information will be available soon." via PCI-SIG pcisig.com/faq? field_category_value%5B%5D=pci_express_7.0&keys= Posted on Jun 11th 2025, 16:27 Reply #12 anonuser57 PrEziWonder how long can be the lines without retimers. With 5.0 it was already an issue, with 6.0 I have seen no improvements, so I assume 7.0 vs 5.0 would need at least 30 if not 50% more redrivers/retimers on the lines (making the whole even more costly). Wonder how big of a role the optical part would play here... which was kinda missed here in the announcement ? PAM4 signaling starting in pcie 6.0. Hopefully that enables higher bandwidth at the same frequency. If all goes well we will see motherboards with pcie 6 slots that can't do pcie 5 but can still do pcie 4. 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