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Computer Science > Emerging Technologies

arXiv:2504.08340 (cs)
[Submitted on 11 Apr 2025]

Title:All-in-Memory Stochastic Computing using ReRAM

Authors:Joao Paulo C. de Lima, Mehran Shoushtari Moghadam, Sercan
Aygun, Jeronimo Castrillon, M. Hassan Najafi, Asif Ali Khan
View a PDF of the paper titled All-in-Memory Stochastic Computing
using ReRAM, by Jo\~ao Paulo C. de Lima and 5 other authors
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    Abstract:As the demand for efficient, low-power computing in
    embedded and edge devices grows, traditional computing methods
    are becoming less effective for handling complex tasks.
    Stochastic computing (SC) offers a promising alternative by
    approximating complex arithmetic operations, such as addition and
    multiplication, using simple bitwise operations, like majority or
    AND, on random bit-streams. While SC operations are inherently
    fault-tolerant, their accuracy largely depends on the length and
    quality of the stochastic bit-streams (SBS). These bit-streams
    are typically generated by CMOS-based stochastic bit-stream
    generators that consume over 80% of the SC system's power and
    area. Current SC solutions focus on optimizing the logic gates
    but often neglect the high cost of moving the bit-streams between
    memory and processor. This work leverages the physics of emerging
    ReRAM devices to implement the entire SC flow in place: (1)
    generating low-cost true random numbers and SBSs, (2) conducting
    SC operations, and (3) converting SBSs back to binary.
    Considering the low reliability of ReRAM cells, we demonstrate
    how SC's robustness to errors copes with ReRAM's variability. Our
    evaluation shows significant improvements in throughput (1.39x,
    2.16x) and energy consumption (1.15x, 2.8x) over state-of-the-art
    (CMOS- and ReRAM-based) solutions, respectively, with an average
    image quality drop of 5% across multiple SBS lengths and image
    processing tasks.

Comments: 7 pages, 5 figures, To appear in DAC 2025
Subjects: Emerging Technologies (cs.ET); Hardware Architecture
          (cs.AR)
Cite as:  arXiv:2504.08340 [cs.ET]
          (or arXiv:2504.08340v1 [cs.ET] for this version)
          https://doi.org/10.48550/arXiv.2504.08340
          Focus to learn more
          arXiv-issued DOI via DataCite (pending registration)

Submission history

From: Asif Ali Khan [view email]
[v1] Fri, 11 Apr 2025 08:11:20 UTC (3,542 KB)
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