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Donate arxiv logo > cs > arXiv:2503.05116 [ ] Help | Advanced Search [All fields ] Search arXiv logo Cornell University Logo [ ] GO quick links * Login * Help Pages * About Computer Science > Hardware Architecture arXiv:2503.05116 (cs) [Submitted on 7 Mar 2025 (v1), last revised 10 Mar 2025 (this version, v2)] Title:Piccolo: Large-Scale Graph Processing with Fine-Grained In-Memory Scatter-Gather Authors:Changmin Shin, Jaeyong Song, Hongsun Jang, Dogeun Kim, Jun Sung, Taehee Kwon, Jae Hyung Ju, Frank Liu, Yeonkyu Choi, Jinho Lee View a PDF of the paper titled Piccolo: Large-Scale Graph Processing with Fine-Grained In-Memory Scatter-Gather, by Changmin Shin and 9 other authors View PDF HTML (experimental) Abstract:Graph processing requires irregular, fine-grained random access patterns incompatible with contemporary off-chip memory architecture, leading to inefficient data access. This inefficiency makes graph processing an extremely memory-bound application. Because of this, existing graph processing accelerators typically employ a graph tiling-based or processing-in-memory (PIM) approach to relieve the memory bottleneck. In the tiling-based approach, a graph is split into chunks that fit within the on-chip cache to maximize data reuse. In the PIM approach, arithmetic units are placed within memory to perform operations such as reduction or atomic addition. However, both approaches have several limitations, especially when implemented on current memory standards (i.e., DDR). Because the access granularity provided by DDR is much larger than that of the graph vertex property data, much of the bandwidth and cache capacity are wasted. PIM is meant to alleviate such issues, but it is difficult to use in conjunction with the tiling-based approach, resulting in a significant disadvantage. Furthermore, placing arithmetic units inside a memory chip is expensive, thereby supporting multiple types of operation is thought to be impractical. To address the above limitations, we present Piccolo, an end-to-end efficient graph processing accelerator with fine-grained in-memory random scatter-gather. Instead of placing expensive arithmetic units in off-chip memory, Piccolo focuses on reducing the off-chip traffic with non-arithmetic function-in-memory of random scatter-gather. To fully benefit from in-memory scatter-gather, Piccolo redesigns the cache and MHA of the accelerator such that it can enjoy both the advantage of tiling and in-memory operations. Piccolo achieves a maximum speedup of 3.28$\times$ and a geometric mean speedup of 1.62$\ times$ across various and extensive benchmarks. Comments: HPCA 2025 Subjects: Hardware Architecture (cs.AR) Cite as: arXiv:2503.05116 [cs.AR] (or arXiv:2503.05116v2 [cs.AR] for this version) https://doi.org/10.48550/arXiv.2503.05116 Focus to learn more arXiv-issued DOI via DataCite Submission history From: Jinho Lee [view email] [v1] Fri, 7 Mar 2025 03:27:33 UTC (1,813 KB) [v2] Mon, 10 Mar 2025 02:41:21 UTC (1,813 KB) Full-text links: Access Paper: View a PDF of the paper titled Piccolo: Large-Scale Graph Processing with Fine-Grained In-Memory Scatter-Gather, by Changmin Shin and 9 other authors * View PDF * HTML (experimental) * TeX Source * Other Formats license icon view license Current browse context: cs.AR < prev | next > new | recent | 2025-03 Change to browse by: cs References & Citations * NASA ADS * Google Scholar * Semantic Scholar a export BibTeX citation Loading... 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