https://www.theregister.com/2025/03/07/dare_europe_risc_v_project/ # # Sign in / up The Register # # # Topics Security Security All SecurityCyber-crimePatchesResearchCSO (X) Off-Prem Off-Prem All Off-PremEdge + IoTChannelPaaS + IaaSSaaS (X) On-Prem On-Prem All On-PremSystemsStorageNetworksHPCPersonal TechCxOPublic Sector (X) Software Software All SoftwareAI + MLApplicationsDatabasesDevOpsOSesVirtualization (X) Offbeat Offbeat All OffbeatDebatesColumnistsScienceGeek's GuideBOFHLegalBootnotesSite NewsAbout Us (X) Special Features Special Features All Special Features Ransomware in Focus The Future of the Datacenter Cybersecurity Month VMware Explore Cloud Infrastructure Month Vendor Voice Vendor Voice Vendor Voice All Vendor Voice RapidScale - AWS Security & Compliance SourceFuse Amazon Web Services (AWS) New Horizon in Cloud Computing Pure Storage Klika Tech HERE and AWS GE Vernova with AWS Google Cloud Data Transformation Google Gemini (X) Resources Resources Whitepapers Webinars & Events Newsletters [hpc] HPC 32 comment bubble on white Do you DARE? Europe bets once again on RISC-V for supercomputing sovereignty 32 comment bubble on white EUR240M found for three-year sprint to develop three chiplets for HPC, AI icon Tobias Mann Fri 7 Mar 2025 // 07:38 UTC # A 38-strong group of tech players have founded a project with the snappy name Digital Autonomy with RISC-V in Europe, aka DARE, that aims to develop processor units to power the continent's supercomputers and other high-performance machines. If you're having deja vu, you're not alone: Europe has been talking about and toying with using RISC-V for supercomputing for some years, even getting far as some silicon, though turned to Arm's architecture for its first exascale system. The continent hasn't given up on RISC-V, though, certainly not with America in the state it's in. The DARE project is supported by the EuroHPC Joint Undertaking and coordinated by the Barcelona Supercomputing Center (BSC-CNS). The project aims to create three chiplets - individual chip dies that can be combined to form complete processor packages - and has already picked leaders for each effort: 1. A vector-math accelerator die tuned for high-performance computing (HPC) workloads, led by Barcelona-based chip designer Openchip 2. A next-gen inference chiplet from Dutch startup Axelera AI 3. A general-purpose processor die, driven by Germany's Codasip "DARE is daring to start from the top of the technological complexity pole and produce European-designed processors chips for supercomputers, paving the way for Europe's digital sovereignty," Osman Unsal, DARE principal investigator at BNC-CNS, said in a statement. The first phase of this six-year endeavor is backed by EUR240 million (PS200 million, $260 million) in funding. DARE has given itself the goal of developing the three above-mentioned RISC-V chiplets in three years. [hpc] Axelera AI, which says it's been awarded EUR61.6 million (PS52 million, $65 million) in funding from EuroHPC, appears to be the furthest along on its journey toward creating a datacenter-class RISC-V chip. While most of its current lineup is focused on running AI models at the network edge, we're told its upcoming Titania chiplet will be designed for server-grade workloads. [hpc] [hpc] On the surface, Axelera's chips follow a similar formula as other AI ASICs, such as Google's tensor processing units. The Dutch outfit's current silicon feature four accelerator cores, each with a matrix multiply-accumulate (MAC) unit, a RISC-V control core to make the accelerator programmable, and some digital signal processors which handle neural network activation functions. Like some other designs we've seen on the market, these MAC units, which are responsible for the bulk of today's AI processing, are embedded in a pool of SRAM enabling efficient streaming and crunching of matrices through the chips; it's classic in-memory processing you see more and more these days. [hpc] CEO Fabrizio Del Maffeo told El Reg Axelera's arrangement of its MAC units allows its quad-core AI processing units to achieve more than 200 INT8 trillion operations per second (TOPS) of inference performance while consuming just 15-20 watts of power. The forthcoming Titania will take this same basic formula but scale it up, with more processing cores on-die and multi-die system-in-package designs. Codasip already offers several 32-bit embedded-class and 64-bit application-grade RISC-V CPU cores, which appear to be aimed at network edge, IoT, and modest personal computing devices. In a press release, the biz said the DARE project would provide it the resources to extend its portfolio to include high performance applications including "AI, big data processing, and supercomputing." [hpc] Little is known about Openchip's vector accelerator. * Under Trump 2.0, Europe's dependence on US clouds back under the spotlight * EU plans to 'mobilize' EUR200B to invest in AI to catch up with US and China * Xen Project delivers solid hypervisor update and keeps working on RISC-V port * NASA's radiation tolerant RISC-V computer lives up to its name after surviving Van Allen belts Europe isn't alone in looking to the royalty free RISC-V ISA as the foundation of technological independence. India has chosen RISC-V in its quest to create highly capable domestic chip designs. China's Alibaba last week unveiled a RISC-V CPU design called the XuanTie C930, which it claims can power PCs to automobiles, amid rumors that Beijing will soon issue guidance that suggests widespread domestic use of the instruction set. While RISC-V is open and permissively licensed, American lawmakers have sometimes called for the US to prevent China's access to the tech. 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