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Dismiss alert {{ message }} OpenXiangShan / XiangShan Public * Notifications You must be signed in to change notification settings * Fork 691 * Star 5.4k Open-source high-performance RISC-V processor xiangshan.cc License View license 5.4k stars 691 forks Branches Tags Activity Star Notifications You must be signed in to change notification settings * Code * Issues 59 * Pull requests 50 * Discussions * Actions * Projects 0 * Wiki * Security * Insights Additional navigation options * Code * Issues * Pull requests * Discussions * Actions * Projects * Wiki * Security * Insights OpenXiangShan/XiangShan master BranchesTags [ ] Go to file Code Folders and files Last Last Name Name commit commit message date Latest commit History 10,536 Commits .github .github coupledL2 @ 24f5582 coupledL2 @ 24f5582 debug debug difftest @ e073982 difftest @ e073982 fudian @ e1bd469 fudian @ e1bd469 huancun @ 3fc7e7e huancun @ 3fc7e7e images images macros/src/main/scala macros/src/main/scala openLLC @ 466bfd7 openLLC @ 466bfd7 project project ready-to-run @ ad1aac3 ready-to-run @ ad1aac3 rocket-chip @ bb4baf8 rocket-chip @ bb4baf8 scripts scripts src src tools/readmemh tools/readmemh utility @ 8de7c42 utility @ 8de7c42 yunsuan @ 3cd12ca yunsuan @ 3cd12ca .gitignore .gitignore .gitmodules .gitmodules .mill-version .mill-version .scalafmt.conf .scalafmt.conf LICENSE LICENSE Makefile Makefile Makefile.test Makefile.test README.md README.md build.sbt build.sbt build.sc build.sc readme.zh-cn.md readme.zh-cn.md scalastyle-config.xml scalastyle-config.xml scalastyle-test-config.xml scalastyle-test-config.xml View all files Repository files navigation * README * License XiangShan XiangShan (Xiang Shan ) is an open-source high-performance RISC-V processor project. Zhong Wen Shuo Ming Zai Ci . Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences. Copyright 2020-2022 by Peng Cheng Laboratory. Docs and slides XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorials and more. * Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io Publications MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced). Artifacts Available Artifacts Evaluated -- Functional Results Reproduced Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video Follow us Wechat/Wei Xin :Xiang Shan Kai Yuan Chu Li Qi [wechat] Zhihu/Zhi Hu :Xiang Shan Kai Yuan Chu Li Qi Weibo/Wei Bo :Xiang Shan Kai Yuan Chu Li Qi You can contact us through our mailing list. All mails from this list will be archived here. Architecture The first stable micro-architecture of XiangShan is called Yanqihu (Yan Qi Hu ) and is on the yanqihu branch, which has been developed since June 2020. The second stable micro-architecture of XiangShan is called Nanhu (Nan Hu ) and is on the nanhu branch. The current version of XiangShan, also known as Kunminghu (Kun Ming Hu ), is still under development on the master branch. The micro-architecture overview of Kunminghu (Kun Ming Hu ) is shown below. xs-arch-kunminghu Sub-directories Overview Some of the key directories are shown below. . +-- src | +-- main/scala # design files | +-- device # virtual device for simulation | +-- system # SoC wrapper | +-- top # top module | +-- utils # utilization code | +-- xiangshan # main design code | +-- transforms # some useful firrtl transforms +-- scripts # scripts for agile development +-- fudian # floating unit submodule of XiangShan +-- huancun # L2/L3 cache submodule of XiangShan +-- difftest # difftest co-simulation framework +-- ready-to-run # pre-built simulation images IDE Support bsp make bsp IDEA make idea Generate Verilog * Run make verilog to generate verilog code. The output file is build/XSTop.v. * Refer to Makefile for more information. Run Programs by Simulation Prepare environment * Set environment variable NEMU_HOME to the absolute path of the NEMU project. * Set environment variable NOOP_HOME to the absolute path of the XiangShan project. * Set environment variable AM_HOME to the absolute path of the AM project. * Install mill. Refer to the Manual section in this guide. * Clone this project and run make init to initialize submodules. Run with simulator * Install Verilator, the open-source Verilog simulator. * Run make emu to build the C++ simulator ./build/emu with Verilator. * Refer to ./build/emu --help for run-time arguments of the simulator. * Refer to Makefile and verilator.mk for more information. Example: make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so Troubleshooting Guide Troubleshooting Guide Acknowledgement The implementation of XiangShan is inspired by several key papers. We list these papers in XiangShan document, see: Acknowledgements. We very much encourage and expect that more academic innovations can be realised based on XiangShan in the future. About Open-source high-performance RISC-V processor xiangshan.cc Topics chisel risc-v microarchitecture Resources Readme License View license Activity Custom properties Stars 5.4k stars Watchers 90 watching Forks 691 forks Report repository Releases 5 tags Packages 0 No packages published Contributors 98 * @poemonsense * @AugustusWillisWang * @Lingrui98 * @ljwljwljwljw * @Lemover * @sashimi-yzh * @jinyue110 * @huxuan0307 * @linjuanZ * @njuallen * @zoujr * @xiaofeibao-xjtu * @Tang-Haojin * @wakafa1 + 84 contributors Languages * Scala 95.9% * Python 3.5% * Other 0.6% Footer (c) 2025 GitHub, Inc. Footer navigation * Terms * Privacy * Security * Status * Docs * Contact * Manage cookies * Do not share my personal information You can't perform that action at this time.