https://github.com/turbo9team/turbo9 Skip to content Navigation Menu Toggle navigation Sign in * Product + Actions Automate any workflow + Packages Host and manage packages + Security Find and fix vulnerabilities + Codespaces Instant dev environments + Copilot Write better code with AI + Code review Manage code changes + Issues Plan and track work + Discussions Collaborate outside of code Explore + All features + Documentation + GitHub Skills + Blog * Solutions For + Enterprise + Teams + Startups + Education By Solution + CI/CD & Automation + DevOps + DevSecOps Resources + Learning Pathways + White papers, Ebooks, Webinars + Customer Stories + Partners * Open Source + GitHub Sponsors Fund open source developers + The ReadME Project GitHub community articles Repositories + Topics + Trending + Collections * Pricing Search or jump to... Search code, repositories, users, issues, pull requests... Search [ ] Clear Search syntax tips Provide feedback We read every piece of feedback, and take your input very seriously. [ ] [ ] Include my email address so I can be contacted Cancel Submit feedback Saved searches Use saved searches to filter your results more quickly Name [ ] Query [ ] To see all available qualifiers, see our documentation. Cancel Create saved search Sign in Sign up You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session. You switched accounts on another tab or window. Reload to refresh your session. Dismiss alert {{ message }} turbo9team / turbo9 Public * Notifications You must be signed in to change notification settings * Fork 2 * Star 42 * Turbo9 - Pipelined 6809 Microprocessor IP License View license 42 stars 2 forks Branches Tags Activity Star Notifications You must be signed in to change notification settings * Code * Issues 0 * Pull requests 0 * Actions * Projects 0 * Security * Insights Additional navigation options * Code * Issues * Pull requests * Actions * Projects * Security * Insights turbo9team/turbo9 This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. main BranchesTags Go to file Code Folders and files Name Name Last commit message Last commit date Latest commit History 31 Commits asm asm c_code c_code docs docs fpga/bit_files fpga/bit_files regress regress rtl rtl sim sim tb tb urtl_asm_src urtl_asm_src .gitignore .gitignore LICENSE.txt LICENSE.txt NOTICE.txt NOTICE.txt README.md README.md View all files Repository files navigation * README * License Turbo9 - A Compact & Efficient Pipelined 6809 Microprocessor IP Turbo9 Logo Soft release v0.9 - This repository is still under construction! --------------------------------------------------------------------- Overview * What is the Turbo9? * What are the target applications? * Why use the 6809 instruction set? Why not RISC? * But wait 6809 is CISC and CISC is bad! The Basics * Key Features * Presentations * Publications * Directory Structure * Third-Party Tools * Current Status * Team Members * Faculty * Contact --------------------------------------------------------------------- What is the Turbo9? The Turbo9 is a pipelined microprocessor IP written in Verilog that executes a superset of the Motorola 6809 instruction set. It is a new modern microarchitecture with 16-bit internal datapaths that balances high performance vs small area / low power. The Turbo9R with a 16-bit memory interface achieves 0.69 DMIPS/MHz which is 3.8 times faster than Motorola's original 8-bit MC6809 implementation. It is an active graduate research project at the Department of Electrical & Computer Engineering at the University of Florida Turbo9 Microarchitecture --------------------------------------------------------------------- What are the target applications? The target applications are SoC sub-blocks or small mixed-signal ASICs that require a compact and efficient microprocessor for programmable high-level control. There are many 32 or 64-bit RISC-V or ARM cores that try to fill this niche, but prove to be inefficient solutions given many of these applications only require 16-bit precision. Turbo9 Target Examples --------------------------------------------------------------------- Why use the 6809 instruction set? Why not RISC? Current industry trends are to adapt 32-bit RISC IP for microcontroller use, however their large 32x32 register files and loosely encoded instructions limit their absolute minimum footprint. So with the goal of a creating a performance and compact microprocessor IP, we need an 16-bit instruction set architecture (ISA). Also, we want an architecture that is capable of running C code effectively. Given these requirements, the Motorola 6809 ISA stands out with its minimal number of registers (shown below), orthogonal instruction set, and powerful indexed and indirect addressing modes that map well to C concepts, such as arrays and pointers. Turbo9 Programming Model --------------------------------------------------------------------- But wait 6809 is CISC and CISC is bad! The 6809 was designed before the definition of RISC and therefore retroactively is classed as a CISC processor. However, the instruction set is actually simpler than many RISC ISAs. The main rule that 6809 instruction set breaks that it is not a "load-store" architecture. It is a simple accumulator architecture where one of its operands is memory. However, the instruction set is very elegant and well thought-through. This presents the challenge of pipelining a CISC processor while remaining as small as possible and attempting to rival performance levels of RISC implementations. To do this, the Turbo9 implements a novel CISC to RISC micro-op decode stage (shown below). Turbo9 Decode Stage --------------------------------------------------------------------- Key Features * Professional Level IP + Modern RTL design techniques & "good practice" o Fully synchronous with single clock o Well defined separation of control and datapath o Separate hierarchy into smaller easier to maintain modules o Design for efficient synthesis into ASIC standard cell libraries & FPGAs o Written in Verilog 2001 for EDA tool compatibility + Optimized for speed, power and area o Design for performance, but not at the expense of power and area o Minimize timing paths for max clock rate o Implement multi-cycle to reduce area / power * Executes a Superset of the Motorola 6809 Instruction Set + Compatible with existing 6809 compilers, assemblers and code base + 16/32-bit multiply & divide instruction extensions * Modern pipelined 16-bit micro-architecture + Instruction prefetch stage + Advanced decode stage (CISC to RISC micro-op translation) + Single/Multi-cycle execute stage + Turbo9R with a 16-bit memory interface achieves 0.69 DMIPS/ MHz o ~3.8 times faster than original 8-bit MC6809 implementation * Pipelined Wishbone bus + Public domain industry standard + Internal separate Program Bus & Data Bus + External shared Program/Data Bus + Adjustable pipeline stages w/ automatic latency adjustment + Different bus configurations available: o Turbo9: 8-bit shared data/program bus o Turbo9S: 16-bit aligned shared data/program bus o Turbo9R: 16-bit non-aligned shared data/program bus o Turbo9GTR: 16-bit non-aligned dual data & program bus * Custom uRTL microcode assembler + written in C + macro based assembler + Verilog output for efficient synthesis into gates, no ROMs + Statistics output + Unlike traditional sequential microcode, it also capable of direct parallel decoding * Professional Verification Testbench + Full self-checking Verilog testbench to verify instruction set + Full randomized regression capable --------------------------------------------------------------------- Presentations * Youtube videos: + Turbo9 - Pipelined 6809 - Overview & uRTL Presentation + Turbo9 - Pipelined 6809 - Benchmarking & Performance + Turbo9 - Pipelined 6809 - Verification & Design Update + Turbo9 - Pipelined 6809 - Introduction & Overview --------------------------------------------------------------------- Publications * Kevin Phillipson's Master's Thesis - A Compact and Efficient Microprocessor IP for SOC Sub-Blocks and Mixed-Signal ASICs --------------------------------------------------------------------- Directory Structure asm/ Assembly code for the Turbo9 docs/ Documents images/ Images c_code/ C code for the Turbo9 build_gcc/ build directory for GCC build_vbcc/ build directory for VBCC byte_sieve_src/ BYTE Sieve source dhrystone_src/ Dhrystone source hello_world_src/ Hello World source lib_gcc/ Library for GCC lib_vbcc/ Library for VBCC fpga/ FPGA project directory bit_files/ .bit files for Arty A7-100T regress/ Nightly regression run directory rtl/ Verilog RTL for micro-architecture urtl/ uRTL microcode for micro-architecture sim/ Simulation run directory tb/ Testbench & Testcases urtl_asm_src/ uRTL microcode assembler source code --------------------------------------------------------------------- Third-Party Tools * Linux environment with C shell, bash, gcc, and make + A Linux environment is required for running and building Turbo9 scripts and tools + We recommend Ubuntu MATE ;-) * Icarus Verilog + Required for running testbench * GTKWave + Required for viewing waveforms from Icarus Verilog * vbcc - portable ISO C compiler + An excellent C compiler for the 6809 / Turbo9 + makefile and library provided in c_code/ * gcc6809 + A port of the GCC compiler for the 6809 + makefile and library provided in c_code/ * CMOC 6809 C language cross-compiler + A very nice C compiler for the 6809 * LWTOOLS cross-dev tools for Motorola 6809 + An excellent assembler for the 6809 + Required for several scripts in asm/ --------------------------------------------------------------------- Current Status The current version of the Turbo9 is thoroughly verified and is capable of running C code. However, we still consider this version v0.9 because we are missing a few items. All the 6809 instructions and addressing modes have been implemented and tested except SYNC and CWAI. The signed versions of the Turbo9's 16-bit divide and multiply need to be completed. Interrupts are partially implemented including SWI and Reset. In order to achieve version 1.0 we require the following: * Finish SYNC and CWAI (6809 instructions) * Finish EDIVS & EMULS (Turbo9 extensions) * Finish Interrupts * Finish Turbo9S bus version * Implement testcases to verify the above Other things to do: * fix stim bench * Verify pipeline bubbles on reset are benign --------------------------------------------------------------------- Team Members Kevin Phillipson Kevin Phillipson * Project Leader * Responsibilities + Microarchitecture design + RTL & Microcode development * 15 years of industry experience in ASIC design * Bachelor's Degree in Electrical Engineering from University of Florida 2008 * Master's Degree in Electrical Engineering from University of Florida in 2022 * Currently pursuing a PhD from University of Florida * Master's Thesis: A Compact & Efficient Microprocessor IP for SoC Sub-Blocks and Mixed-Signal ASICs Michael Rywalt Michael Rywalt * Principal Contributor * Responsibilities + Custom uRTL microcode assembler + Verification & Tools * 15 years of industry experience in ASIC design * Bachelor's Degree of science in Computer Science and software Engineering from Florida Institute of Technology 2008 * Currently pursuing a Master's Degree in Electrical Engineering from University of Florida * Master's Thesis: Verification of a compact & efficient microprocessor IP --------------------------------------------------------------------- Faculty Dr. Greg Stitt Dr. Greg Stitt * Associate Professor * NSF Center for Space, High-Performance, and Resilient Computing (SHREC) * Research interests: Embedded systems with an emphasis in synthesis, compilers, reconfigurable computing, hardware/software co-design * Website: www.gstitt.ece.ufl.edu Dr. Eric M. Schwartz Dr. Eric M. Schwartz * Instructional Professor * Machine Intelligence Laboratory Director * Research interests: Robotics, embedded systems, controls, autonomous mobile agents * Website: mil.ufl.edu/ems Dr. Martin Margala Dr. Martin Margala * Director of School of Computing and Informatics - University of Louisiana Lafayette * Academia: Former Professor and Chair of the Electrical and Computer Engineering Department at the University of Massachusetts Lowell * Website: people.cmix.louisiana.edu/margala/ --------------------------------------------------------------------- Contact You may contact us at team[at]turbo9[dot]org. Thank you! About Turbo9 - Pipelined 6809 Microprocessor IP Resources Readme License View license Activity Stars 42 stars Watchers 1 watching Forks 2 forks Report repository Releases No releases published Packages 0 No packages published Contributors 2 * @dundee256 dundee256 * @turbo9team turbo9team Languages * Verilog 71.9% * C 17.2% * Assembly 5.2% * Tcl 3.5% * Shell 0.8% * Makefile 0.8% * Other 0.6% Footer (c) 2024 GitHub, Inc. Footer navigation * Terms * Privacy * Security * Status * Docs * Contact * Manage cookies * Do not share my personal information You can't perform that action at this time.