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Dismiss alert {{ message }} verilator / verilator Public * Notifications * Fork 529 * Star 2.2k * Verilator open-source SystemVerilog simulator and lint system verilator.org License LGPL-3.0 license 2.2k stars 529 forks Branches Tags Activity Star Notifications * Code * Issues 299 * Pull requests 18 * Actions * Security * Insights Additional navigation options * Code * Issues * Pull requests * Actions * Security * Insights verilator/verilator This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. master BranchesTags Go to file Code Folders and files Last Last Name Name commit commit message date Latest commit History 6,947 Commits .devcontainer .devcontainer .github .github bin bin ci ci docs docs examples examples include include nodist nodist src src test_regress test_regress .clang-format .clang-format .clang-tidy .clang-tidy .codacy.yml .codacy.yml .gitattributes .gitattributes .gitignore .gitignore Artistic Artistic CITATION.cff CITATION.cff CMakeLists.txt CMakeLists.txt CPPLINT.cfg CPPLINT.cfg Changes Changes LICENSE LICENSE Makefile.in Makefile.in README.rst README.rst codecov.yml codecov.yml configure.ac configure.ac install-sh install-sh verilator-config-version.cmake.in verilator-config-version.cmake.in verilator-config.cmake.in verilator-config.cmake.in verilator.pc.in verilator.pc.in View all files Repository files navigation * README * LGPL-3.0 license badge1 badge2 badge3 badge4 badge5 badge6 badge7 badge8 Welcome to Verilator Welcome to Verilator, the fastest Verilog/SystemVerilog simulator. + Accepts Verilog or SystemVerilog + Performs lint code-quality checks Logo + Compiles into multithreaded C++, or SystemC + Creates XML to front-end your own tools Fast + Outperforms many closed-source commercial verilator multithreaded performance simulators + Single- and multithreaded output models Widely Used + Wide industry and academic deployment verilator usage + Out-of-the-box support from Arm and RISC-V vendor IP Community Driven & Openly Licensed + Guided by the CHIPS Alliance and Linux verilator community Foundation + Open, and free as in both speech and beer + More simulation for your verification budget Commercial Support Available + Commercial support contracts verilator support + Design support contracts + Enhancement contracts What Verilator Does Verilator is invoked with parameters similar to GCC or Synopsys's VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the "Verilated" code. These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators. Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend Icarus Verilog for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you. Performance Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). Verilator has typically similar or better performance versus closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator, Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus, Verilator gives you the best simulation cycles/dollar. Installation & Documentation For more information: * Verilator installation and package directory structure * Verilator manual (HTML), or Verilator manual (PDF) * Subscribe to Verilator announcements * Verilator forum * Verilator issues Support Verilator is a community project, guided by the CHIPS Alliance under the Linux Foundation. We appreciate and welcome your contributions in whatever form; please see Contributing to Verilator. Thanks to our Contributors and Sponsors. Verilator also supports and encourages commercial support models and organizations; please see Verilator Commercial Support. Related Projects * GTKwave - Waveform viewer for Verilator traces. * Icarus Verilog - Icarus is a full-featured interpreted Verilog simulator. If Verilator does not support your needs, perhaps Icarus may. Open License Verilator is Copyright 2003-2024 by Wilson Snyder. (Report bugs to Verilator Issues.) Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. See the documentation for more details. About Verilator open-source SystemVerilog simulator and lint system verilator.org Topics cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator Resources Readme License LGPL-3.0 license Activity Custom properties Stars 2.2k stars Watchers 74 watching Forks 529 forks Report repository Releases 157 tags Packages 0 No packages published Contributors 198 * @wsnyder * @gezalore * @RRozak * @yTakatsukasa * @toddstrader * @kbieganski * @kamilrakoczy * @jcoiner * @wallento * @kboronski-ant * @kiryk * @donlon * @phb * @mglb + 184 contributors Languages * C++ 44.7% * SystemVerilog 38.4% * Perl 11.1% * C 3.0% * Python 1.5% * Shell 0.5% * Other 0.8% Footer (c) 2024 GitHub, Inc. Footer navigation * Terms * Privacy * Security * Status * Docs * Contact * Manage cookies * Do not share my personal information You can't perform that action at this time.