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Tech Industry TSMC unveils 1.6nm process technology with backside power delivery, rivals Intel's competing design News By Anton Shilov published 25 April 2024 TSMC goes angstrom-class nodes. * * * * * * * Comments (4) TSMC fire at new plant (Image credit: TSMC) TSMC announced its leading-edge 1.6nm-class process technology today, a new A16 manufacturing process that will be the company's first Angstrom-class production node and promises to outperform its predecessor, N2P, by a significant margin. The technology's most important innovation will be its backside power delivery network (BSPDN). Just like TSMC's 2nm-class nodes (N2, N2P, and N2X), the company's 1.6nm-class fabrication process will rely on gate-all-around (GAA) nanosheet transistors, but unlike the current and next-generation nodes, this one uses backside power delivery dubbed Super Power Rail. Transistor and BSPDN innovations enable tangible performance and efficiency improvements compared to TSMC's N2P: the new node promises an up to 10% higher clock rate at the same voltage and a 15%-20% lower power consumption at the same frequency and complexity. In addition, the new technology could enable 7%-10% higher transistor density, depending on the actual design. TSMC (Image credit: TSMC) The most important innovation of TSMC's A16 process, which was unveiled at the company's North American Technology Symposium 2024, is the introduction of the Super Power Rail (SPR), a sophisticated backside power delivery network (BSPDN). This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks. Backside power delivery will be implemented into many upcoming process technologies as it allows for an increase in transistor density and improved power delivery, which affects performance. Meanwhile, there are several ways to implement a BSPDN. TSMC's Super Power Rail plugs the backside power delivery network to each transistor's source and drain using a special contact that also reduces resistance to get the maximum performance and power efficiency possible. From a production perspective, this is one of the most complex BSPDN implementations and is more complex than Intel's Power Via. TSMC (Image credit: TSMC) The choice of backside power rail implementation is perhaps why TSMC decided not to add this feature to its N2P and N2X process technologies, as it would make using the production nodes considerably more expensive. Meanwhile, by offering a 1.6nm-class node with GAA nanosheet transistors and SPR as well as 2nm-class nodes with GAAFETs only, the company will now have two distinct nodes that will not compete with each other directly but offer distinctive advantages for different customers. TSMC (Image credit: TSMC) The production timeline for A16 indicates that volume production of A16 will commence in the second half of 2026. Therefore, actual A16-made products will likely debut in 2027. This timeline positions A16 to potentially compete with Intel's 14A node, which will be the Intel's most advanced node at the time. Stay on the Cutting Edge Join the experts who read Tom's Hardware for the inside track on enthusiast PC tech news -- and have for over 25 years. We'll send breaking news and in-depth reviews of CPUs, GPUs, AI, maker hardware and more straight to your inbox. [ ][ ]Contact me with news and offers from other Future brands[ ]Receive email from us on behalf of our trusted partners or sponsors[Sign me up] By submitting your information you agree to the Terms & Conditions and Privacy Policy and are aged 16 or over. Anton Shilov Anton Shilov Social Links Navigation Freelance News Writer Anton Shilov is a Freelance News Writer at Tom's Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. More about tech industry A Russian flag on the pin of a microchip Russian media claims server and storage supply has returned to pre-sanctions levels despite ongoing restrictions Jensen Huang with Sam Altman and Greg Brockman Nvidia CEO hand-delivers world's fastest AI system to OpenAI, again -- first DGX H200 given to Sam Altman and Greg Brockman Latest Best Flash Drives Best Flash Drives 2024: Fast, Roomy, Pocketable USB Storage See more latest > See all comments (4) [ ] 4 Comments Comment from the forums * usertests So it's a half node that introduces backside power delivery. The power reduction is where it's at. Those handhelds need every bit they can get. Reply * CerianK Just in case anyone needs to hear it, Angstrom-class refers to any process node moving forward where it would otherwise be necessary to include a decimal point in the node descriptor, so 16 A, rather than 1.6 nm. That should work just fine for the next 10+ years, barring any sudden paradigm shift (given the number of advanced technologies vying for an opportunity to displace silicon at smaller scales). Reply * JamesJones44 usertests said: So it's a half node that introduces backside power delivery. The power reduction is where it's at. Those handhelds need every bit they can get. The issue is people who don't understand resolutions and distance will be demanding 8K on those handhelds by then and will sap any energy savings gained. Reply * usertests JamesJones44 said: The issue is people who don't understand resolutions and distance will be demanding 8K on those handhelds by then and will sap any energy savings gained. I think Steam Deck is leading the pack of x86 handhelds in sales... with a 720p screen. I can't imagine most buyers caring about more than 1080p anytime soon. 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