https://arxiv.org/abs/2404.10076

Skip to main content
Cornell University
We gratefully acknowledge support from the Simons Foundation, member
institutions, and all contributors. Donate
 
arxiv logo > cs > arXiv:2404.10076
[                    ]

Help | Advanced Search

[All fields        ]
Search
arXiv logo
Cornell University Logo
[                    ] GO
quick links

  * Login
  * Help Pages
  * About

Computer Science > Hardware Architecture

arXiv:2404.10076 (cs)
[Submitted on 15 Apr 2024]

Title:Field-Programmable Gate Array Architecture for Deep Learning:
Survey & Future Directions

Authors:Andrew Boutros, Aman Arora, Vaughn Betz
View a PDF of the paper titled Field-Programmable Gate Array
Architecture for Deep Learning: Survey & Future Directions, by Andrew
Boutros and 2 other authors
View PDF HTML (experimental)

    Abstract:Deep learning (DL) is becoming the cornerstone of
    numerous applications both in datacenters and at the edge.
    Specialized hardware is often necessary to meet the performance
    requirements of state-of-the-art DL models, but the rapid pace of
    change in DL models and the wide variety of systems integrating
    DL make it impossible to create custom computer chips for all but
    the largest markets. Field-programmable gate arrays (FPGAs)
    present a unique blend of reprogrammability and direct hardware
    execution that make them suitable for accelerating DL inference.
    They offer the ability to customize processing pipelines and
    memory hierarchies to achieve lower latency and higher energy
    efficiency compared to general-purpose CPUs and GPUs, at a
    fraction of the development time and cost of custom chips. Their
    diverse high-speed IOs also enable directly interfacing the FPGA
    to the network and/or a variety of external sensors, making them
    suitable for both datacenter and edge use cases. As DL has become
    an ever more important workload, FPGA architectures are evolving
    to enable higher DL performance. In this article, we survey both
    academic and industrial FPGA architecture enhancements for DL.
    First, we give a brief introduction on the basics of FPGA
    architecture and how its components lead to strengths and
    weaknesses for DL applications. Next, we discuss different styles
    of DL inference accelerators on FPGA, ranging from model-specific
    dataflow styles to software-programmable overlay styles. We
    survey DL-specific enhancements to traditional FPGA building
    blocks such as logic blocks, arithmetic circuitry, and on-chip
    memories, as well as new in-fabric DL-specialized blocks for
    accelerating tensor computations. Finally, we discuss hybrid
    devices that combine processors and coarse-grained accelerator
    blocks with FPGA-like interconnect and networks-on-chip, and
    highlight promising future research directions.

Subjects: Hardware Architecture (cs.AR)
Cite as:  arXiv:2404.10076 [cs.AR]
          (or arXiv:2404.10076v1 [cs.AR] for this version)
          https://doi.org/10.48550/arXiv.2404.10076
          Focus to learn more
          arXiv-issued DOI via DataCite

Submission history

From: Andrew Boutros [view email]
[v1] Mon, 15 Apr 2024 18:28:10 UTC (1,975 KB)
Full-text links:

Access Paper:

    View a PDF of the paper titled Field-Programmable Gate Array
    Architecture for Deep Learning: Survey & Future Directions, by
    Andrew Boutros and 2 other authors
  * View PDF
  * HTML (experimental)
  * TeX Source
  * Other Formats

license icon view license
Current browse context:
cs.AR
< prev   |   next >
new | recent | 2404
Change to browse by:
cs

References & Citations

  * NASA ADS
  * Google Scholar
  * Semantic Scholar

a export BibTeX citation Loading...

BibTeX formatted citation

x
[loading...          ]
Data provided by:

Bookmark

BibSonomy logo Reddit logo
(*) Bibliographic Tools

Bibliographic and Citation Tools

[ ] Bibliographic Explorer Toggle
Bibliographic Explorer (What is the Explorer?)
[ ] Litmaps Toggle
Litmaps (What is Litmaps?)
[ ] scite.ai Toggle
scite Smart Citations (What are Smart Citations?)
( ) Code, Data, Media

Code, Data and Media Associated with this Article

[ ] Links to Code Toggle
CatalyzeX Code Finder for Papers (What is CatalyzeX?)
[ ] DagsHub Toggle
DagsHub (What is DagsHub?)
[ ] GotitPub Toggle
Gotit.pub (What is GotitPub?)
[ ] Links to Code Toggle
Papers with Code (What is Papers with Code?)
[ ] ScienceCast Toggle
ScienceCast (What is ScienceCast?)
( ) Demos

Demos

[ ] Replicate Toggle
Replicate (What is Replicate?)
[ ] Spaces Toggle
Hugging Face Spaces (What is Spaces?)
[ ] Spaces Toggle
TXYZ.AI (What is TXYZ.AI?)
( ) Related Papers

Recommenders and Search Tools

[ ] Link to Influence Flower
Influence Flower (What are Influence Flowers?)
[ ] Connected Papers Toggle
Connected Papers (What is Connected Papers?)
[ ] Core recommender toggle
CORE Recommender (What is CORE?)

  * Author
  * Venue
  * Institution
  * Topic

( ) About arXivLabs

arXivLabs: experimental projects with community collaborators

arXivLabs is a framework that allows collaborators to develop and
share new arXiv features directly on our website.

Both individuals and organizations that work with arXivLabs have
embraced and accepted our values of openness, community, excellence,
and user data privacy. arXiv is committed to these values and only
works with partners that adhere to them.

Have an idea for a project that will add value for arXiv's community?
Learn more about arXivLabs.

Which authors of this paper are endorsers? | Disable MathJax (What is
MathJax?)

  * About
  * Help

  * Click here to contact arXiv Contact
  * Click here to subscribe Subscribe

  * Copyright
  * Privacy Policy

  * Web Accessibility Assistance
  * arXiv Operational Status
    Get status notifications via email or slack