https://www.righto.com/2024/03/idt-gate-array.html
Ken Shirriff's blog
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Inside an unusual 7400-series chip implemented with a gate array
When I look inside a chip from the popular 7400 series, I know what
to expect: a fairly simple die, implemented in a straightforward,
cost-effective way. However, when I looked inside a military-grade
chip built by Integrated Device Technology (IDT)4 I found a very
unexpected layout: over 1500 transistors in an orderly matrix. Even
stranger, most of the die is wasted: less than 20% of these
transistors are used, forming scattered circuits connected by thin
metal wires.
In this blog post, I look at this chip in detail, describe its gates,
and explain how it implements the "1-of-4" decoder function. I also
discuss why it sometimes makes sense to build chips with a gate array
design such as this, despite the inefficiency.
A photo of the tiny silicon die in its package. This chip is the IDT
54FCT139ALB dual 1-of-4 decoder. Click this image (or any other) for
a larger version.
A photo of the tiny silicon die in its package. This chip is the IDT
54FCT139ALB dual 1-of-4 decoder. Click this image (or any other) for
a larger version.
In the photo below, you can see the silicon die in more detail, with
the silicon appearing pink. The main circuitry is implemented in the
nine rows that form the gate array, a grid of 1584 transistors. The
tiny dark rectangles are transistors of two types, NMOS and PMOS,
that work together to implement CMOS logic circuits. At this scale,
the metal wiring is visible as faint gray lines and smudges, but most
of the transistors are unconnected. Surrounding the gate array are 22
input/output (I/O) blocks each with a square bond pad. As with the
transistors, many of these I/O blocks are unused. Fourteen of these
bond pads have tiny metal bond wires (the thick black lines) that
connect the silicon die to the chip's external pins. Finally, the
pairs of bond wires at the center left and center right provide
ground and power connections for the chip.
Closeup die photo.
Closeup die photo.
The photo below zooms in on three rows of circuitry in the chip. The
large dark rectangles are pairs of transistors, with two lines of
transistors in each row of circuitry. At the top and bottom of each
row, the thick horizontal white lines are metal wiring that provides
power and ground. In each row, one line of transistors holds PMOS
transistors, next to the power wiring, while the other line holds
NMOS transistors, next to the ground wiring. (The orientation flips
in each successive row, so it isn't obvious which transistors are
which unless you check the power connections at the end of the row.)
A closeup of the die.
A closeup of the die.
The transistors are wired into gates by the metal layers, the white
lines. The gates are connected by horizontal and vertical wiring
using the wiring channels between the rows. This wiring style is very
similar to standard-cell logic. However, unlike standard-cell logic,
the underlying transistor grid is fixed, resulting in wasted
transistors. In the image above, most of the transistors in the
middle row are used, while the top row is unused and the bottom row
is mostly unused.
The diagram below shows the structure of one of the transistor
blocks, which contains two tall, thin MOS transistors. The vertical
metal contacts connect to the sources and drains of the transistors,
with the two transistors sharing the middle contact. (On an
integrated circuit, the source and drain of a transistor are
identical, so it is arbitrary which side is the source and which is
the drain.) The short horizontal metal contacts at the top connect to
the gates of the two transistors; the gates are made of polysilicon,
which is barely visible in the die photo. The gates partition the
active silicon (green), forming the transistors. The gate width is
approximately 1 um.
A block of two transistors as they appear on the die, along with a
diagram showing the structure. The bar indicates a length of 10 um.
A block of two transistors as they appear on the die, along with a
diagram showing the structure. The bar indicates a length of 10 um.
NAND gate
In this section, I'll explain the construction of one of the NAND
gates on the die. The NAND gate below uses four transistors, two NMOS
transistors on the top and two PMOS transistors on the bottom. The
white lines are the metal wiring, forming two layers. Most of the
wiring (including power and ground) is in the lower (M1) layer. The
slightly wider and darker vertical segments are the upper (M2) layer.
The circles connect the metal layers when they join, or connect the
metal layer to the underlying silicon or polysilicon. With two metal
layers, it's a bit tricky to see how the wiring is connected. The A
and B inputs each connect to two transistor gates. The transistor
group at the top is connected to ground on the right, with the output
on the left. The transistor group on the bottom is connected to Vcc
on the left and right, with the output in the middle. This has the
effect of putting the upper transistors in series and the lower
transistors in parallel.
A NAND gate on the die.
A NAND gate on the die.
Below, I've drawn the schematic of the NAND gate. On the left, the
layout of the schematic matches the die layout above. On the right,
I've redrawn the schematic with a more traditional layout. To
understand its operation, note that a PMOS transistor (top on the
right schematic) turns on when the input is low, while an NMOS
transistor (bottom on the right) turns on when the input is high.
When both inputs are high, the two NMOS transistors turn on,
connecting ground to the output, pulling it low. When either input is
low, one of the PMOS transistors turns on, pulling the output high.
Thus, the circuit implements the NAND function. The NMOS and PMOS
transistors operate in a complementary fashion, giving CMOS
(Complementary MOS) its name.
Schematic of a NAND gate.
Schematic of a NAND gate.
NOR gate
In this section, I'll explain the layout of one of the NOR gates on
the die, shown below. This gate is twice as large as the previous
NAND gate so it can provide twice the output current.1 The NOR gate
uses eight transistors, four PMOS transistors in the upper half and
four NMOS transistors in the lower half. (Note that Vcc and ground
are flipped compared to the previous gate, as are the NMOS and PMOS
transistors.) The two transistors in each block are wired in parallel
to produce more current for the output. (A out is the same signal as
A in, exiting the block at the top to connect to other circuitry.)
A NOR gate on the die.
A NOR gate on the die.
The schematic below shows the wiring of the eight transistors. The
schematic layout corresponds to the physical layout to make it easier
to map between the image and the schematic. The upper transistor
groups are wired in series, while the lower transistor groups are
wired in parallel.
Schematic corresponding to the gate above.
Schematic corresponding to the gate above.
The schematic below has been redrawn to make the functionality
clearer, and the parallel transistors have been removed. If either
input is high, one of the NMOS transistors on the bottom will turn on
and pull the input low. If both inputs are low, the two PMOS
transistors will turn on and pull the input high. This provides the
desired NOR function.
Simplified NOR gate schematic.
Simplified NOR gate schematic.
Note that the NAND and NOR gates have similar but opposite
schematics. In the NAND gate, the NMOS transistors are in series
while the PMOS transistors are in parallel. In the NOR gate, the
roles of the transistors are swapped.
The chip's circuit
The chip I examined is a "dual 1-of-4 decoder with enable".2 The
decoding function takes a two-bit input and selects one of four
output lines depending on the binary value. The enable line must be
low to activate this operation; otherwise all four output lines are
disabled. The chip contains two of these decoders, which is why it is
called a dual decoder. In total, the chip contains 18 logic gates,3
so it is very simple, even by 1990s standards.
I reverse-engineered the chip and created the schematic below,
showing one of the dual units. Each NAND gate matches one of the four
input possibilities to drive one of the four outputs. The NOR gates
support the ENABLE signal, blocking the outputs unless ENABLE is
active (i.e. low).
Reverse-engineered schematic of half the chip.
Reverse-engineered schematic of half the chip.
The chip uses a general-purpose I/O block (below) for each pin, that
can be used as an input or an output depending on how it is wired.
Each block contains two large drive transistors: an NMOS transistor
to pull the output low and a PMOS transistor to pull the output high.
The I/O block has separate control lines for the two output
transistors. (At the bottom of the image below, two thin metal wires
drive the high-side and low-side transistors.) This permits tri-state
logic: if neither transistor is energized, the output is left
floating. The gate array drives the output transistors with
high-current inverter, constructed from multiple transistors in
parallel. (This is why the schematic shows more inverters than may
seem necessary.)
One of the 22 I/O blocks on the die. Each I/O block is associated
with a bond pad, where a bond wire can be connected to an external
pin.
One of the 22 I/O blocks on the die. Each I/O block is associated
with a bond pad, where a bond wire can be connected to an external
pin.
When used as an input, the pad is wired to the surrounding circuitry
slightly differently, connecting to input protection diodes (not
shown on the schematic). Thus, the functionality of the I/O blocks
can be changed by modifying the metal layers, without changing the
underlying silicon.
Some 7400-series history
The earliest logic integrated circuits used resistors and transistors
internally, so they were called RTL (Resistor Transistor Logic), but
RTL had significant performance problems. RTL was rapidly replaced by
Diode Transistor Logic (DTL) and then Transistor Transistor Logic
(TTL). In 1964, Texas Instruments created a line of TTL integrated
circuits for military applications called the SN5400 series. This was
shortly followed by the commercial-grade SN7400 series.
The 7400 series of integrated circuits was inexpensive, fast, and
easy to use. The line started with simple logic circuits such as four
NAND gates on a chip, and moved into more complex chips such as
counters, shift registers, and ALUs. The 7400 series became very
popular in the 1970s and 1980s, used by electronics hobbyists and
high-performance minicomputers alike. These chips became essential
building blocks and "glue" logic for microcomputers, heavily used in
the Apple II for instance.
The original 7400 series branched into dozens of families with
different performance characteristics but the same functionality. The
74LS (low-power Schottky) family, for instance, became very popular
as it both improved speed and reduced power consumption. In the
mid-1970s, 7400-series chips were introduced that used CMOS circuitry
instead of TTL for dramatically lower power consumption. This CMOS
family, the 74C series, was followed by numerous other CMOS families.
That brings us to the chip I examined, a member of IDT's 74FCT (Fast
CMOS TTL-compatible) line of chips, introduced in the mid-1980s.
(Specifically, it is in the 54FCT family because it handles a wider
temperature range.) These chips used advanced CMOS technology to
provide high speed, low power consumption, and as a military option,
radiation tolerance.
Conclusions
Why would you make a chip in this inefficient way, using a gate array
that wastes most of the die area? The motivation is that most of the
design cost can be shared across many different part types. Each step
of integrated circuit processing requires an expensive mask for
photolithography. With a gate array, all chip types use the same
underlying silicon and transistors, with custom masks just for the
two metal layers. In comparison, a fully custom chip might require
eight custom masks, which costs much more. The tradeoff is that gate
array chips are larger so the manufacturing cost is higher per
device.5 Thus, a gate array design is better when selling chips in
relatively small quantities, while a custom design is cheaper when
mass-producing chips.6 IDT focused on the high-performance and
military market rather than the commodity chip market, so gate arrays
were a good fit.
One last thing. The packaging of this chip is very interesting since
it is mounted on a multi-chip module. The module also contains two
Atmel EEPROMs. Presumably the decoder chip decodes address bits to
select one of the EEPROMs.
The multi-chip module containing the decoder chip along with an
AT28HC64 EPROM on either side.
The multi-chip module containing the decoder chip along with an
AT28HC64 EPROM on either side.
Thanks to Don S. for providing the chip. Follow me on Twitter
@kenshirriff or RSS for updates. I've also started experimenting with
Mastodon recently as @oldbytes.space@kenshirriff.
Notes and references
1. Properly sizing the transistors in a gate is important for
performance. Since the transistors in the gate array are all the
same size, multiple transistors are used in parallel to get the
desired current. The 1999 book Logical Effort describes a
methodology for maximizing the performance of CMOS circuits by
correctly sizing the transistors. -
2. The part number is "IDT 54FCT139ALB". "54" indicates the chip
operates under an enhanced temperature range of -55degC to +125degC.
The "A" indicates the chip is 35% faster than the base series
(but not as fast as "C"). "L" indicates the chip is packaged in a
leadless chip carrier, the square package shown at the top of the
article. Finally, "B" indicates the chip was tested according to
military standards: MIL-STD-883, Class B. -
3. The chip contains 18 logic gates according to the functional
schematic in the datasheet (below). The implementation actually
uses 52 logic gates by my count (2x26) because the implementation
doesn't exactly match the schematic. In particular, the datasheet
shows three-input NAND gates, but the chip uses a NAND gate and a
NOR gate along with inverters. The chip also has additional
inverters to drive the output transistors in each I/O block.
Schematic of the chip from the datasheet.
Schematic of the chip from the datasheet.
-
4. Integrated Device Technology was a spinoff from Hewlett Packard
that started in 1980. IDT built advanced CMOS chips including
fast static RAM and microprocessors (bit-slice and MIPS). It
became part of Renesas in 2018. A very detailed 1986 profile of
IDT is here. IDT's logo is pretty cool, combining a chip wafer
and calculus.
The logo of Integrated Device Technology.
The logo of Integrated Device Technology.
Here's how the logo looks on the die:
Closeup of the die showing the IDT logo.
Closeup of the die showing the IDT logo.
The die also has the initials of the designers, along with some
mysterious symbols. One looks like the Chinese character "Zheng ".
(Update: based on a Twitter comment, these symbols are probably
tally marks, indicating the revision count for each mask.)
-Closeups of two parts of the die.
Closeups of two parts of the die.
5. Integrated circuit manufacturing is partitioned into the "front
end of line", where the transistors are created on the silicon
wafer, and the "back end of line", where the metal wiring is put
on top to connect the transistors. With a gate array
construction, the front end of line steps create generic gate
array wafers. The back end of line steps then connect the
transistors as desired for a particular component. The gate array
wafers can be produced in large quantities and stored, and then
customized for specific products in smaller quantities as needed.
This reduces the time to supply a particular chip type since only
the back end of line process needs to take place. -
6. The IDT High-Speed CMOS Logic Design Guide briefly mentions the
gate array design. The FCT family was built from two sizes of
gate arrays, "4004" for smaller chips and "8000" for larger
chips. Later, IDT shrunk the original "Z-step" gate arrays to
smaller, higher-performance "Y-step" arrays. They then customized
some of the devices to create the "W-step" devices. Looking at
the markings on the die, we see that this chip uses the "4004Y"
gate array.
The die shows gate slice 4004Y and part 4139Y (indicating 54139
or 74139). The numbers are slightly obscured by a bond wire.
The die shows gate slice 4004Y and part 4139Y (indicating 54139
or 74139). The numbers are slightly obscured by a bond wire.
-
# #
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Labels: chips, electronics, reverse-engineering
3 comments:
[bla]
Steve S. said...
"Reverse-engineered schematic of half the chip" has an error...
March 30, 2024 at 12:28 PM [icon_delet]
[bla]
Anonymous said...
a dot
March 30, 2024 at 1:31 PM [icon_delet]
[blo]
Ken Shirriff said...
Thanks Steve, I've fixed the schematic.
March 30, 2024 at 2:06 PM [icon_delet]
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