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Design Tools 3. MicroBlaze V Processor microblazev-microcontroller AMD MicroBlaze(tm) V Processor A Flexible and Efficient RISC-V Processor. * Overview * Processor Details Overview The AMD MicroBlaze(tm) V processor is a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs. The MicroBlaze V processor is based on a 32-bit RISC-V instruction set architecture (ISA). It allows developers to leverage the open-source RISC-V software ecosystem, is hardware compatible with the classic MicroBlaze processor, and is fully integrated in the Vivado(tm) and Vitis(tm) tools design flow. The MicroBlaze V processor is designed to be highly modular with a configurable architecture suitable for embedded systems applications. Developers can target the MicroBlaze V processor to any AMD adaptive SoC or FPGA device supported by the Vivado Design Suite at no extra cost. --------------------------------------------------------------------- risc-v-logo RISC-V is an open-source standard instruction set architecture (ISA) that is managed by the non-profit RISC-V Foundation. AMD has been a member since 2020. +-------------------------------------------------------------------+ | Key Capabilities | |-------------------------------------------------------------------| |Based on RISC-V Open-Source ISA | | | | * Backed by a comprehensive ecosystem of software and solutions | | throughout the industry | | * Enables easy hardware migration for existing MicroBlaze | | processor designs and software portability for RISC-V designs | | * Configurable ISA support for RV32IMAFC Base Integer Instruction| | Set with optional: | | + Multiplication and division ("M" extension) | | + Atomic instructions ("A" extension) | | + Floating-point ("F" extension) | | + Code compression ("C" extension) | | + Bit manipulation ("Zba", "Zbb", "Zbc", "Zbs" extensions) | | * Utilizes code compression to significantly reduce code size and| | save design memory | | | |Efficient Architecture at its Core | | | | * Offers three selectable configurations: microcontroller, | | real-time processor, and application processor* | | * Provides build options to optimize area and/or performance | | * Incorporates safety measures like dual-core lockstep and triple| | modular redundancy (TMR) for safety-critical systems | | | |High Degree of Design Flexibility | | | | * Offers a fully-integrated design flow in the Vivado and Vitis | | tools, identical to the MicroBlaze processor design flow | | * Compatible with any AMD adaptive SoC or FPGA supported in the | | Vivado design tools | | * Offers a user-friendly experience with either a graphic user | | interface (GUI) or command line interface (CLI) | | * Reduces system component count and shortens development time | | with a wide range of optimized IP available to deploy an | | integrated MicroBlaze V processor subsystem in the programable | | logic | | | |* Microcontroller configuration available now in Early Access; | |real-time and application processor configurations on the roadmap | +-------------------------------------------------------------------+ microblaze-v-stack-diagram --------------------------------------------------------------------- amd-microblaze-logo Leverage the tried, tested, and trusted MicroBlaze(tm) processor from AMD. With its versatile uses and consistent performance, it's a dependable choice for numerous applications. Learn More Processor Details Key Drag n' Drop Peripherals +----------------------------------------------------------------------+ |General Purpose | I/O | Video | Memory | Networking | |----------------+-----------+-------------+------------+--------------| | * Multichannel| * UART | * HDMI | * DDR | * Ethernet | | DMA | * USB 2.0| Camera/ | * Quad SPI| Subsystem | | * Streaming | * SPI | Display | * SDRAM | * Controller| | FIFO | * GPIO | Interface| | Area | | * Timer / | * PWM | * MIPI-CSI,| | Network | | Watchdog | | MIPI-DSI | | | | * Mutex / | | * Video DMA| | | | Mailbox | | | | | +----------------------------------------------------------------------+ Example Design Configurations +------------------------------------------------------------------------+ | |Microcontroller | | | | | | * 32-bit Processor Core (RV32IMAFC) | | | * JTAG Debug Interface | |[microblazev-microcontroller]| * Tightly Coupled Local Memory | |Click to enlarge | * SPI controller | | | * I2C Controller | | | * UART | | | * Interrupt Controller | | | * Timer | | | * GPIO | |-----------------------------+------------------------------------------| |On the Roadmap |Real-Time Processor | |-----------------------------+------------------------------------------| |On the Roadmap |Application Processor | +------------------------------------------------------------------------+ Subscribe to the latest news from AMD * Facebook * Twitter * Instagram * Linkedin * Subscriptions * Youtube * Twitch Company * About AMD * Management Team * Corporate Responsibility * Careers * Contact Us News & Events * Newsroom * Events * Blogs * Media Library Community * Support * Developer * Red Team Partners * Developer Central * AMD Partner Hub * Partner Resource Library * Authorized Distributors Investors * Investor Relations * Financial Information * Board of Directors * Governance Documents * SEC Filings * Terms and Conditions * Privacy * Trademarks * Statement on Forced Labor * Fair & Open Competition * UK Tax Strategy * Cookies Policy * Cookie Settings (c) 2023 Advanced Micro Devices, Inc. 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