https://verilogtorouting.org/

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The Verilog to Routing (VTR) project provides open-source CAD tools
for FPGA architecture and CAD research. This project, along with the
benchmark suites, is released under the MIT license. This means that
you are free to use, modify, and distribute the software and
benchmark files, subject to the terms and conditions of the MIT
license.

VPR Placement Device Floorplan & Placement

Open source CAD tools enable the investigation of new FPGA
architectures and CAD algorithms, which are not possible with
closed-source tools.

The VTR design flow takes as input a Verilog description of a digital
circuit, and a description of the target FPGA architecture. It then
perfoms:

  * Elaboration & Synthesis (ODIN II)
  * Logic Optimization & Technology Mapping (ABC)
  * Packing, Placement, Routing & Timing Analysis (VPR)

to produce FPGA speed and area results. VTR can also produce the
information required for bitstream generation to target real FPGA
devices.

FPGA Routing Switchbox FPGA Routing Switchbox

VTR is flexible and can taget a wide range of hypothetical,
commercial-like and commercial FPGA architectures, and includes
benchmark designs suitable for evaluating FPGA architectures.

For more information see the documentation.

VPR Optimization: Placement & Routing
Placement
Logical Connections
Routing Utilization

Verilog to Routing

  * Verilog to Routing
  * [email protected]

  * verilog-to-routing

Open source tools for FPGA architecture and CAD research