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STH ServeTheHome Advertisement [INS::INS] STH STH * Forums * AI * Server + Server Systems + Server CPUs + Accelerators + Server Motherboards + Server Chassis + Other Components * 5G Edge * Storage * Networking * Workstation + Workstation Processors + Workstation Motherboards * Software + Operating Systems + Server Applications + Virtualization * Guides + Buyer's Guides + Tips + Top Hardware Components for TrueNAS / FreeNAS NAS Servers + Top Hardware Components for pfSense Appliances + Top Hardware Components for napp-it and Solarish NAS Servers + Top Picks for Windows Server 2016 Essentials Hardware + The DIY WordPress Hosting Server Hardware Guide [ ][Search] Home News Intel Shows 8 Core 528 Thread Processor with Silicon Photonics * News Intel Shows 8 Core 528 Thread Processor with Silicon Photonics By Patrick Kennedy - August 29, 2023 6 Facebook Twitter Pinterest Linkedin Email Print Intel 8 Core 528 Thread Chip With Optical Networking For DARPAIntel 8 Core 528 Thread Chip With Optical Networking For DARPA Intel had a cool technology on display at Hot Chips 2023, beyond just server chips. It had a direct mesh-to-mesh optical fabric. What might also be interesting is the 8-core processor with 66 threads per core. Again, please excuse typos, these are being done live. Intel Shows the First Direct Mesh-to-Mesh Optical Fabric The key motivation behind this was the DARPA HIVE program for hyper-sparse data. Intel Direct Mesh To Mesh Optical Fabric_Page_03Intel Direct Mesh To Mesh Optical Fabric_Page_03 When Intel profiled the workloads that DARPA was looking at, they found they were massively parallel. Still, they had poor cache line utilization and things like big long out-of-order pipelines were not well utilized. Intel Direct Mesh To Mesh Optical Fabric_Page_04Intel Direct Mesh To Mesh Optical Fabric_Page_04 Here is an interesting one. Intel has a 66-thread-per-core processor with 8 cores in a socket (528 threads?) The cache apparently is not well used due to the workload. This is a RISC ISA not x86. Intel Direct Mesh To Mesh Optical Fabric_Page_05Intel Direct Mesh To Mesh Optical Fabric_Page_05 Intel is packing these into 16 sockets in a single OCP compute thread and using optical networking. Here is the die architecture. Each core has multi-threaded pipelines. Intel Direct Mesh To Mesh Optical Fabric_Page_06Intel Direct Mesh To Mesh Optical Fabric_Page_06 The high-speed I/O chips bridge the electrical to optical capabilities of the chip. Here is the 10-port cut-through router being used. Intel Direct Mesh To Mesh Optical Fabric_Page_07Intel Direct Mesh To Mesh Optical Fabric_Page_07 Here is the on-die network where the routers are placed. Half of the 16 routers are there just to provide more bandwidth to the high-speed I/O. On-packaged EMIBs are being used for the physical connection layer. Intel Direct Mesh To Mesh Optical Fabric_Page_08Intel Direct Mesh To Mesh Optical Fabric_Page_08 Going off-die, each chip uses silicon photonics to drive its optical networking. With this, the connections between cores can happen directly between chips even if they are not in the same chassis without adding switches and NICs. Intel Direct Mesh To Mesh Optical Fabric_Page_09Intel Direct Mesh To Mesh Optical Fabric_Page_09 These chips are being packaged as a multi-chip package with EMIB. Having silicon photonics engines added a few other challenges of going from package to strands of fiber. Intel Direct Mesh To Mesh Optical Fabric_Page_10Intel Direct Mesh To Mesh Optical Fabric_Page_10 Here is the optical performance. Intel Direct Mesh To Mesh Optical Fabric_Page_11Intel Direct Mesh To Mesh Optical Fabric_Page_11 In terms of power, this was done in an 8-core 75W CPU. More than half of the power here is being used by silicon photonics. Intel Direct Mesh To Mesh Optical Fabric_Page_12Intel Direct Mesh To Mesh Optical Fabric_Page_12 Here is the simulated to measured workload performance scaling. Intel Direct Mesh To Mesh Optical Fabric_Page_13Intel Direct Mesh To Mesh Optical Fabric_Page_13 Here is the actual die photograph and confirmation that this is being done on TSMC 7nm. Intel Direct Mesh To Mesh Optical Fabric_Page_14Intel Direct Mesh To Mesh Optical Fabric_Page_14 Here is what the package and test board looks like: Intel Direct Mesh To Mesh Optical Fabric_Page_15Intel Direct Mesh To Mesh Optical Fabric_Page_15 This was done in 7nm and work is still happening on this in the lab. Intel Direct Mesh To Mesh Optical Fabric_Page_16Intel Direct Mesh To Mesh Optical Fabric_Page_16 Final Words It was interesting to see that Intel did not use the pluggable connector it showed off at Innovation 2022. It seems like this might have been built before that project was ready. This was assisted by Ayar Labs on the optical side. Perhaps the big item is the 66 threads per core! That is a huge figure. I think folks will enjoy that stat. Just as a heads-up, we are going to have a video later this week on the Intel Xeon Max (Sapphire Rapids with HBM2e onboard) and will even show it booting a hypervisor and running a VM all from HBM, without DDR5 installed. Intel has a lot of exotic chips either as projects or in production. Subscribe to our 250K+ YouTube channel to see all the fun things we get to do with chips like Xeon Max there. [INS::INS] * TAGS * DARPA * Intel * Silicon Photonics Previous articleLightelligence Hummingbird Low-Latency Optical Connection Engine Next articleMoffett Antoum AI Inference Accelerator at Hot Chips 2023 Patrick Kennedy https://www.servethehome.com Patrick has been running STH since 2009 and covers a wide variety of SME, SMB, and SOHO IT topics. Patrick is a consultant in the technology industry and has worked with numerous large hardware and storage vendors in the Silicon Valley. The goal of STH is simply to help users find some information about server, storage and networking, building blocks. If you have any helpful information please feel free to post on the forums. RELATED ARTICLESMORE FROM AUTHOR Intel Granite Rapids Top Hot Chips 2023 Server CPUs Intel Granite Rapids Xeon Held at Hot Chips 2023 Intel E Core Focus HC35_Page_12 Server CPUs Intel Xeon E-Cores for Next Gen Sierra Forest and More at Hot Chips 2023 Intel Granite Rapids And Sierra Forest Next Gen CPUs HC35_Page_06 Server CPUs Intel on Changing its Xeon CPU Architecture at Hot Chips 2023 6 COMMENTS 1. Stephen Beets August 29, 2023 At 3:18 pm Damn sakes. 66 threads? Per core? Is that a typo or have Intel really built such a thing? If that is, in fact, not a typo, that's one damn big-ass processor (or maybe WIDE-ass since 8 cores is on the puny end but with 528 total threads, that makes it quite wide in terms of number of concurrent "channels/lanes" per core). Judging by the pics provided, the package, while big, doesn't seem quite "mainframe-sized" enough to me for 528 threads to really be viable. Also, unless I missed it, there doesn't appear to be any mention of what this RISC monster is being called. I'm assuming it isn't ARM and i860 and i960 are both deader than a roast turkey on Thanksgiving Day. Very cool, though. 2. antonio August 29, 2023 At 5:39 pm @Stephen Beets -- I'm assuming this is some kind of funky research prototype. Probably doesn't get a marketing name any time soon. https://dmccreary.medium.com/ intels-incredible-piuma-graph-analytics-hardware-a2e9c3daf8d8 is from a few years ago about this HW. 3. Doug's Reptile August 29, 2023 At 8:33 pm Perhaps some fruits from the Risc-V good will Intel has been spending out? Nice little micro services box. Mainframe like really. 4. abstractexchange August 29, 2023 At 9:49 pm how about performance per watt of this photonic CPU ? 5. Yamamoto August 30, 2023 At 2:43 am From my understanding, this is purpose built processor to perform large graph traversal. On graph traversal tasks, each thread just load then conditional store and ALU or other singleton resource of the processor is rarely used and efficiency is scaled well by increasing just execution unit. I remember similar purpose built CPU, Sun Niagara processor which is designed solery for web server tasks, and one floating point unit is shared by 8 cores (32 hyperthreads) 6. J August 30, 2023 At 10:27 am @Stephen Beets, since the threads for the target workload issue a memory load every few commands, which takes on the order of 100 clock cycles to complete, they spend the vast majority of the time idle. having 66 threads per core allows those memory loads to execute in parallel. as the data for different threads arrives on the order of every clock cycle, commands are dispatched to the execution units nearly every cycle, so the execution units achieve a high overall utilization. LEAVE A REPLY [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] Please enter your comment! [ ] Please enter your name here [ ] You have entered an incorrect email address! Please enter your email address here [ ] [ ]Save my name, email, and website in this browser for the next time I comment. [ ] [ ]Sign me up for the STH newsletter! [Post Comment] [ ] [ ] [ ] [ ] [ ] [ ] [ ] D[ ] This site uses Akismet to reduce spam. Learn how your comment data is processed. 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