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STH ServeTheHome Advertisement [INS::INS] STH STH * Forums * AI * Server + Server Systems + Server CPUs + Accelerators + Server Motherboards + Server Chassis + Other Components * 5G Edge * Storage * Networking * Workstation + Workstation Processors + Workstation Motherboards * Software + Operating Systems + Server Applications + Virtualization * Guides + Buyer's Guides + Tips + Top Hardware Components for TrueNAS / FreeNAS NAS Servers + Top Hardware Components for pfSense Appliances + Top Hardware Components for napp-it and Solarish NAS Servers + Top Picks for Windows Server 2016 Essentials Hardware + The DIY WordPress Hosting Server Hardware Guide [ ][Search] Home Server Server CPUs Three New AMD EPYC Genoa-X SKUs with up to 48MB L3 cache... * Server * Server CPUs Three New AMD EPYC Genoa-X SKUs with up to 48MB L3 cache per Core or 1.1GB Total By Patrick Kennedy - July 10, 2023 2 Facebook Twitter Pinterest Linkedin Email Print AMD EPYC Genoa X Package 1AMD EPYC Genoa X Package 1 AMD has three new SKUs as part of its newest high-cache chip lineup. What might surprise our readers is the core counts as AMD is going after two very different markets with the new AMD Genoa-X series. While many may expect a 96 cores 1.1GB of L3 cache behemoth, others may not be expecting a part with 48MB of L3 cache. AMD EPYC Genoa-X SKU List Still built around the same Zen 4 architecture that we saw with the original AMD EPYC Genoa, the new chips add 3D V-Cache. For folks wondering, this is very much in line with the AMD EPYC Milan-X. AMD EPYC Genoa X Launch HighlightsAMD EPYC Genoa X Launch Highlights The high-end 12x CCD version is the AMD EPYC 9684X at $14,756 list price. This 96-core chip has 1152MB of L3 cache which may even not be the craziest. AMD EPYC Genoa X Launch SKUsAMD EPYC Genoa X Launch SKUs AMD also has two chips, seemingly made for per-core licensing (e.g. 16 cores for Windows Server and 32 cores for VMware.) The AMD EPYC 9384X is a 32-core part with 768MB of L3 cache at $5529. Perhaps the crazier one is the AMD EPYC 9184X which has the same 768MB of L3 cache for a total of 48MB of L3 cache per core. The $4928 list price of that part may seem like a lot, but if you are optimizing on per-core performance, that extra L3 cache can have a huge dollar impact. Final Words AMD has a strategy where it now has three server CPU lines in the same socket. The mainstream Genoa, the high-core count, Bergamo, and the high-cache Genoa-X. As we have mentioned previously, the big win will be a future part combining reduced base-die cache / high core count chips with L3 cache stacked. We think it is at least a generation away, but Bergamo-Next-X is going to be a fascinating part. AMD EPYC Genoa X Package 2AMD EPYC Genoa X Package 2 As you would expect, we will have a full review with benchmarks when the embargo lifts. [INS::INS] * TAGS * amd * EPYC * Genoa * genoa-x Previous articleioSafe 1522+ NAS Review Synology Powered Fireproof and Waterproof NAS Patrick Kennedy https://www.servethehome.com Patrick has been running STH since 2009 and covers a wide variety of SME, SMB, and SOHO IT topics. Patrick is a consultant in the technology industry and has worked with numerous large hardware and storage vendors in the Silicon Valley. The goal of STH is simply to help users find some information about server, storage and networking, building blocks. If you have any helpful information please feel free to post on the forums. RELATED ARTICLESMORE FROM AUTHOR IoSafe 1522 Plus NAS Front Angle 1 Storage ioSafe 1522+ NAS Review Synology Powered Fireproof and Waterproof NAS Minisforum UM790 Pro Front Angle Workstation Minisforum UM790 Pro Review Big Upgrade to a Small AMD System AMD EPYC Bergamo Package 1 Server CPUs AMD EPYC Bergamo Launch SKUs 2 COMMENTS 1. AustinP July 10, 2023 At 10:13 am "The AMD EPYC 9384X is a 32-core part with 768GB of L3 cache" 768GB of cache per CPU is certainly very, very impressive! (and quite likely should have the G replaced with an M) 2. GuyisIT July 10, 2023 At 12:02 pm I've been curious about this since AMD first launched the -X lineup: What would application performance look like if they stacked HBM memory (maybe even not a full stack) on top of the IO die. Whether that replaces the L3 cache or is an L4 cache. LEAVE A REPLY [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] Please enter your comment! [ ] Please enter your name here [ ] You have entered an incorrect email address! Please enter your email address here [ ] [ ]Save my name, email, and website in this browser for the next time I comment. [ ] [ ]Sign me up for the STH newsletter! [Post Comment] [ ] [ ] [ ] [ ] [ ] [ ] [ ] D[ ] This site uses Akismet to reduce spam. Learn how your comment data is processed. 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