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Computer Science > Hardware Architecture

arXiv:2305.04760 (cs)
[Submitted on 8 May 2023]

Title:Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for
Domain-Specific Accelerator Plug-In

Authors:Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca
Benini
Download a PDF of the paper titled Cheshire: A Lightweight,
Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator
Plug-In, by Alessandro Ottaviano and 3 other authors
Download PDF

    Abstract: Power and cost constraints in the internet-of-things
    (IoT) extreme-edge and TinyML domains, coupled with increasing
    performance requirements, motivate a trend toward heterogeneous
    architectures. These designs use energy-efficient
    application-class host processors to coordinate
    compute-specialized multicore accelerators, amortizing the
    architectural costs of operating system support and external
    communication. This brief presents Cheshire, a lightweight and
    modular 64-bit Linux-capable host platform designed for the
    seamless plug-in of domain-specific accelerators. It features a
    unique low-pin-count DRAM interface, a last-level cache
    configurable as scratchpad memory, and a DMA engine enabling
    efficient data movement to or from accelerators or DRAM. It also
    provides numerous optional IO peripherals including UART, SPI,
    I2C, VGA, and GPIOs. Cheshire's synthesizable RTL description,
    comprising all of its peripherals and its fully digital DRAM
    interface, is available free and open-source. We implemented and
    fabricated Cheshire as a silicon demonstrator called Neo in
    TSMC's 65nm CMOS technology. At 1.2 V, Neo achieves clock
    frequencies of up to 325 MHz while not exceeding 300 mW in total
    power on data-intensive computational workloads. Its RPC DRAM
    interface consumes only 250 pJ/B and incurs only 3.5 kGE in area
    for its PHY while attaining a peak transfer rate of 750 MB/s at
    200 MHz.

Comments: 5 pages, 11 figures, submitted to an IEEE journal for
          possible publication
Subjects: Hardware Architecture (cs.AR)
Cite as:  arXiv:2305.04760 [cs.AR]
          (or arXiv:2305.04760v1 [cs.AR] for this version)
          https://doi.org/10.48550/arXiv.2305.04760
          Focus to learn more
          arXiv-issued DOI via DataCite

Submission history

From: Thomas Benz [view email]
[v1] Mon, 8 May 2023 15:08:51 UTC (2,209 KB)
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    Download a PDF of the paper titled Cheshire: A Lightweight,
    Linux-Capable RISC-V Host Platform for Domain-Specific
    Accelerator Plug-In, by Alessandro Ottaviano and 3 other authors
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