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Latest commit @Tang-Haojin Tang-Haojin top-down: add rob head type into consideration (#1999) ... 6ed1154 Mar 26, 2023 top-down: add rob head type into consideration (#1999) * top-down: add rob head type into consideration * top-down: put counters into EnableTopDown scope 6ed1154 Git stats * 7,309 commits Files Permalink Failed to load latest commit information. Type Name Latest commit message Commit time .github ci: use checkout@v3 instead of v2 (#1942) February 27, 2023 09:50 debug bump difftest & mkdir for wave/perf for local-ci script's run-mode (# ... February 21, 2023 12:49 difftest @ ea83bb7 submodules: track commits on master branch (#1988) March 22, 2023 12:29 fudian @ 43474be Switch to asynchronous reset for all modules (#1867) January 2, 2023 08:58 huancun @ d5b306c submodules: track commits on master branch (#1988) March 22, 2023 12:29 images misc: fix typo in nanhu arch figure (#1552) May 11, 2022 17:12 project update sbt version March 3, 2019 16:54 ready-to-run @ ff39f36 ci: bump ready-to-run nemu November 21, 2022 21:29 rocket-chip @ 254ebf7 fix for chipsalliance/rocket-chip#2967 (#1562) May 31, 2022 09:22 scripts top-down: add rob head type into consideration (#1999) March 26, 2023 16:08 src top-down: add rob head type into consideration (#1999) March 26, 2023 16:08 tools/readmemh misc: update PCL information (#899) July 24, 2021 23:26 utility @ c83eac5 submodules: track commits on master branch (#1988) March 22, 2023 12:29 .gitignore dcache: setup way predictor framework (#1857) January 4, 2023 22:34 .gitmodules Separate Utility submodule from XiangShan (#1861) December 25, 2022 14:52 .mill-version build.sc: remove testOnly (#843) June 26, 2021 16:26 LICENSE Add MulanPSL-2.0 License (#824) June 4, 2021 09:06 Makefile test: add example of chiseltest's unit-test and generating verilog fo... February 14, 2023 09:52 Makefile.test test: add example of chiseltest's unit-test and generating verilog fo... February 14, 2023 09:52 README.md Update README.md for micro paper (#1817) November 5, 2022 09:19 build.sbt Add sbt build support (#857) July 3, 2021 09:34 build.sc test: add example of chiseltest's unit-test and generating verilog fo... February 14, 2023 09:52 readme.zh-cn.md Update README.md for micro paper (#1817) November 5, 2022 09:19 scalastyle-config.xml first commit February 6, 2019 11:06 scalastyle-test-config.xml first commit February 6, 2019 11:06 View code [ ] XiangShan Docs and slides Publications MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology Follow us Architecture Sub-directories Overview IDE Support bsp IDEA Generate Verilog Run Programs by Simulation Prepare environment Run with simulator Troubleshooting Guide Acknowledgement README.md XiangShan XiangShan (Xiang Shan ) is an open-source high-performance RISC-V processor project. Zhong Wen Shuo Ming Zai Ci . Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences. Copyright 2020-2022 by Peng Cheng Laboratory. Docs and slides XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more. * Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io Publications MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced). Artifacts Available Artifacts Evaluated -- Functional Results Reproduced Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video Follow us Wechat/Wei Xin :Xiang Shan Kai Yuan Chu Li Qi [wechat] Zhihu/Zhi Hu :Xiang Shan Kai Yuan Chu Li Qi Weibo/Wei Bo :Xiang Shan Kai Yuan Chu Li Qi You can contact us through our mail list. All mails from this list will be archived to here. Architecture The first stable micro-architecture of XiangShan is called Yanqihu (Yan Qi Hu ) on the yanqihu branch, which has been developed since June 2020. The second stable micro-architecture of XiangShan is called Nanhu (Nan Hu ) on the nanhu branch. The current version of XiangShan, also known as Kunminghu (Kun Ming Hu ), is still under development on the master branch. The micro-architecture overview of Nanhu (Nan Hu ) is shown below. xs-arch-nanhu Sub-directories Overview Some of the key directories are shown below. . +-- src | +-- main/scala # design files | +-- device # virtual device for simulation | +-- system # SoC wrapper | +-- top # top module | +-- utils # utilization code | +-- xiangshan # main design code | +-- xstransforms # some useful firrtl transforms +-- scripts # scripts for agile development +-- fudian # floating unit submodule of XiangShan +-- huancun # L2/L3 cache submodule of XiangShan +-- difftest # difftest co-simulation framework +-- ready-to-run # pre-built simulation images IDE Support bsp make bsp IDEA make idea Generate Verilog * Run make verilog to generate verilog code. The output file is build/XSTop.v. * Refer to Makefile for more information. Run Programs by Simulation Prepare environment * Set environment variable NEMU_HOME to the absolute path of the NEMU project. * Set environment variable NOOP_HOME to the absolute path of the XiangShan project. * Set environment variable AM_HOME to the absolute path of the AM project. * Install mill. Refer to the Manual section in this guide. * Clone this project and run make init to initialize submodules. Run with simulator * Install Verilator, the open-source Verilog simulator. * Run make emu to build the C++ simulator ./build/emu with Verilator. * Refer to ./build/emu --help for run-time arguments of the simulator. * Refer to Makefile and verilator.mk for more information. Example: make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so Troubleshooting Guide Troubleshooting Guide Acknowledgement In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below. Sub-module Source Detail L2 Cache/ Sifive Our new L2/L3 design are inspired by LLC block-inclusivecache Sifive's block-inclusivecache. Diplomacy/ We reused the Diplomacy framework and TileLink Rocket-chip TileLink utility that exist in rocket-chip to negotiate bus. We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license. About Open-source high-performance RISC-V processor Topics chisel3 risc-v microarchitecture Resources Readme License View license Stars 3.4k stars Watchers 76 watching Forks 421 forks Releases 2 tags Packages 0 No packages published Contributors 41 * @poemonsense * @AugustusWillisWang * @Lingrui98 * @ljwljwljwljw * @sashimi-yzh * @Lemover * @jinyue110 * @njuallen * @linjuanZ * @zoujr * @wakafa1 + 30 contributors Languages * Scala 93.5% * Python 4.7% * Other 1.8% Footer (c) 2023 GitHub, Inc. Footer navigation * Terms * Privacy * Security * Status * Docs * Contact GitHub * Pricing * API * Training * Blog * About You can't perform that action at this time. You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session.