https://github.com/the-aerospace-corporation/satcat5 Skip to content Toggle navigation Sign up * Product + Actions Automate any workflow + Packages Host and manage packages + Security Find and fix vulnerabilities + Codespaces Instant dev environments + Copilot Write better code with AI + Code review Manage code changes + Issues Plan and track work + Discussions Collaborate outside of code + Explore + All features + Documentation + GitHub Skills + Blog * Solutions + For + Enterprise + Teams + Startups + Education + By Solution + CI/CD & Automation + DevOps + DevSecOps + Case Studies + Customer Stories + Resources * Open Source + GitHub Sponsors Fund open source developers + The ReadME Project GitHub community articles + Repositories + Topics + Trending + Collections * Pricing [ ] * # In this repository All GitHub | Jump to | * No suggested jump to results * # In this repository All GitHub | Jump to | * # In this organization All GitHub | Jump to | * # In this repository All GitHub | Jump to | Sign in Sign up {{ message }} the-aerospace-corporation / satcat5 Public * Notifications * Fork 10 * Star 142 SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network. License LGPL-3.0, GPL-3.0 licenses found Licenses found LGPL-3.0 COPYING.LESSER GPL-3.0 COPYING 142 stars 10 forks Star Notifications * Code * Issues 0 * Pull requests 0 * Actions * Projects 0 * Security * Insights More * Code * Issues * Pull requests * Actions * Projects * Security * Insights the-aerospace-corporation/satcat5 This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository. main Switch branches/tags [ ] Branches Tags Could not load branches Nothing to show {{ refName }} default View all branches Could not load tags Nothing to show {{ refName }} default View all tags Name already in use A tag already exists with the provided branch name. Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. Are you sure you want to create this branch? Cancel Create 2 branches 11 tags Code * Local * Codespaces * Clone HTTPS GitHub CLI [https://github.com/t] Use Git or checkout with SVN using the web URL. [gh repo clone the-ae] Work fast with our official CLI. Learn more. * Open with GitHub Desktop * Download ZIP Sign In Required Please sign in to use Codespaces. Launching GitHub Desktop If nothing happens, download GitHub Desktop and try again. Launching GitHub Desktop If nothing happens, download GitHub Desktop and try again. Launching Xcode If nothing happens, download Xcode and try again. Launching Visual Studio Code Your codespace will open once ready. There was a problem preparing your codespace, please try again. Latest commit @ooterness @Teque5 ooterness and Teque5 Release 2.3.0 (#21) ... bbba3e4 Feb 15, 2023 Release 2.3.0 (#21) * Release 2.3.0 * Update doc/CHANGELOG.md Co-authored-by: Teque5 * Update doc/ARTY_A7.md Co-authored-by: Teque5 * Update doc/CHANGELOG.md Co-authored-by: Teque5 * Update examples/README.md Co-authored-by: Teque5 --------- Co-authored-by: Teque5 bbba3e4 Git stats * 19 commits Files Permalink Failed to load latest commit information. Type Name Latest commit message Commit time .github Release 1.2.2. (#4) November 10, 2020 14:27 doc Release 2.3.0 (#21) February 14, 2023 17:46 examples Release 2.3.0 (#21) February 14, 2023 17:46 project Release 2.3.0 (#21) February 14, 2023 17:46 sim Release 2.3.0 (#21) February 14, 2023 17:46 src Release 2.3.0 (#21) February 14, 2023 17:46 test Release 2.3.0 (#21) February 14, 2023 17:46 .gitignore PR-19 hotfix: Simplify build process and update ARTY_A7 readme. (#20) January 26, 2023 11:13 COPYING Initial release 1.0.0. December 11, 2019 16:06 COPYING.LESSER Initial release 1.0.0. December 11, 2019 16:06 Jenkinsfile Release 2.3.0 (#21) February 14, 2023 17:46 Makefile Release 2.3.0 (#21) February 14, 2023 17:46 README.md Release 2.2.0 (#15) December 20, 2022 14:23 start_docker.sh Release 2.2.0 (#15) December 20, 2022 14:23 View code [ ] SatCat5 Introduction Switch Capabilities What Is Provided Getting Started Further Reading Folder Structure Contributing Changelog Patents Copyright Notice README.md SatCat5 Introduction SatCat5 Logo SatCat5 is FPGA gateware that implements a low-power, mixed-media Ethernet switch. It also includes embedded software libraries to help microcontrollers interact with Ethernet networks. A SatCat5 switch is functionally equivalent to commercially available, unmanaged Ethernet switches for home use. However, it also supports lower-speed connections to the same network using I2C, SPI, or UART. These lower-rate data links (commonly used in simple, low-cost, low-power microcontrollers) allow nearly any device to participate in the same local communication network, regardless of its capability level. Like any Ethernet switch, this one has multiple ports; each port is a point-to-point link from the switch to a network device, which could be a PC, a microcontroller, or even another switch. Power draw required for the switch itself is well under 1 watt. The main expected users of this project are cubesat and smallsat developers. By encouraging everyone to use this technology, we create a mutually-compatible ecosystem that will make it easier to develop new small-satellite payloads, and simultaneously make it easier to integrate those payloads into vehicles. For more information on SatCat5 and cubesats, refer to our SmallSat 2020 publication. However, we think the same technology might be useful to other embedded systems, including Internet-of-Things systems that want to integrate microcontrollers onto a full-featured LAN. Switch Capabilities Example network with microcontrollers and other nodes A major goal of the SatCat5 project is to support a variety of endpoints, from simple microcontrollers to a full-fledged PC, all connected to the same Ethernet network. A complete listing of supported interfaces is available here. The list includes the usual 10/100/1000 Mbps "Media Independent Interfaces" (RMII, RGMII, SGMII) as well as media and physical-layer options that aren't usually used with Ethernet (I2C, SPI, UART). The latter options are typically lower speed (1-10 Mbps), but use physical layer protocols that are more amenable to use with simple microcontrollers. All interfaces transmit and receive standard Ethernet Frames. Switch operation can be designed in an HDL-only environment - however, many designs use soft-core embedded processors to provide higher level functionality such as handling of ARP, ICMP, IP, and UDP messages, along with switch or attached device configuration. What Is Provided This project is effectively a set of building blocks, ready to be used to build and connect to your own custom Ethernet switch. The switch can be optimized to your needs, tailored to your preferred platform, port count, interface types, etc. In addition to these building blocks, we include several reference designs that showcase many of the available features. The easiest way to get started is with the Digilent Arty A7, a low-cost FPGA development board. We've included a reference design and companion documentation that specifically targets this board. PMOD connector pinouts are chosen to be directly compatible with off-the-shelf USB-UART adapters. Other reference designs include the prototype that we built to develop, test, and demonstrate the SatCat5 switch. It is intended to run on many off-the-shelf FPGA development boards, using an FMC port to attached to a custom PCB. The custom PCB includes Ethernet transceivers, PMOD connectors, and other I/O. SatCat5 also includes software libraries targeting both baremetal and POSIX systems for: * Sending and receiving Ethernet frames. * Sending and receiving ARP, ICMP, IP, and UDP messages. * Configuring a managed SatCat5 Ethernet switch. * Configuring various SatCat5 I/O peripherals (e.g., I2C, MDIO, SPI, or UART). A simple memory-mapped interface for configuration registers called ConfigBus was designed and can be found in the majority of designs. It is much lighter weight than AXI4-Lite as it is designed for small control registers. More information, including Microblaze libraries, control over Ethernet, and user register setup can be found in its documentation. Getting Started If you'd like to build the Arty example design, you'll need the Vivado Design Suite. We've tested with version 2015.4, 2016.3, and 2019.1, but it should work as-is with most other versions as well. Once it's installed, simply run "make arty_35t" in the root folder. (Or follow the equivalent steps under Windows.) If you'd like to build your own design, create a new top-level VHDL file and add the following: * Any number of port_xx blocks. (e.g., port_spi, port_uart, port_rgmii, etc.) * At least one switch_core block. * One switch_aux block. This provides error-reporting, status LEDs, and other niceties. * Clock generation. Check the documentation for selected port type (s) to see what's needed. Another option for user designs on Xilinx platforms is the Vivado IP Integrator. SatCat5 natively supports this block-diagram based flow and offers wrappers for the vast majority of compatible blocks. The drag-and-drop nature and single-wire bus interface connections make this a good choice for complex designs. Further Reading Once started and familiar with the basics of SatCat5, it is highly recommended to read through the Frequently Asked Questions (FAQs). This contains a huge swath of tips, guidance, clarifications, and potential issues. Advice and tips on good development operations (DevOps) practices, including automated and hardware-in-the-loop testig, can also be found in the DevOps documentation Folder Structure * doc: Documentation and associated images. All documentation is linked somewhere in this README. * example: Example designs for specific hardware platforms * project: Scripts and project files for specific vendor tools + libero: Building Microsemi designs in Libero. (Tested with version 12.3.) + modelsim: Running VHDL simulations in ModelSim. (Tested with version 10.0a.) + vivado: Packagine IP-cores, building, or simulating Xilinx designs in Vivado. (Tested with Vivado version 2019.1.) + yosis: Building Lattice designs using Yosis. * sim: Simulation and verification of the design + cpp: Unit tests for the embedded software libraries. + matlab: MATLAB/Octave scripts used to generate certain lookup tables. + test: Test data for various unit-test simulations. + vhdl: VHDL unit tests for individual functional blocks. * src: Source code for the core SatCat5 design + cpp: C/C++ software libraries targeting various platforms o hal_ublaze: Microblaze-specific hardware abstraction layer (HAL). o hal_posix: Linux HAL intended to be used to run embedded unit tests on a Linux host. o satcat5: Cross-platform libraries for connecting to and configuring an Ethernet network. + python: Python libraries for connecting to raw-Ethernet / Ethernet-over-UART ports and remote ConfigBus control. + vhdl: VHDL implementation of functional blocks o common: Location of most functional blocks, targets all platforms. o lattice: Platform-specific VHDL for the Lattice iCE40. o microsemi: Platform-specific VHDL for the Microsemi Polarfire. o xilinx: Platform-specific VHDL for Xilinx 7-series and Ultrascale platforms. * test: Additional testing, including the prototype reference design + chat_client: A demo application that implements chatroom functions using raw Ethernet frames. + log_viewer: A demo application for viewing Chat/Log messages from example designs. + pi_wire: A tool for connecting to SatCat5 with a Raspberry Pi. Contributing We encourage you to contribute to SatCat5! Please check out the guidelines here for information on how to submit bug reports and code changes. Changelog A log of major changes per SatCat5 release can be found in the Change Log. Patents Portions of SatCat5 are patented under US11055254B2. In accordance with SatCat5's LGPL license agreement, we grant a royalty-free license for use of this technology. Refer to section 11 of the GPLv3 license for details. Copyright Notice Copyright 2019, 2020, 2021, 2022 The Aerospace Corporation This file is part of SatCat5. SatCat5 is free software: you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. SatCat5 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with SatCat5. If not, see https://www.gnu.org/licenses/ . About SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network. Resources Readme License LGPL-3.0, GPL-3.0 licenses found Licenses found LGPL-3.0 COPYING.LESSER GPL-3.0 COPYING Stars 142 stars Watchers 7 watching Forks 10 forks Releases 11 v2.3.0 Latest Feb 15, 2023 + 10 releases Contributors 6 * @ooterness * @aero-utter * @bradh * @Teque5 * @hecrabbs * @giulianahofheins Languages * VHDL 57.6% * C++ 31.9% * Tcl 3.7% * Stata 3.0% * Python 2.6% * MATLAB 0.6% * Other 0.6% Footer (c) 2023 GitHub, Inc. Footer navigation * Terms * Privacy * Security * Status * Docs * Contact GitHub * Pricing * API * Training * Blog * About You can't perform that action at this time. You signed in with another tab or window. Reload to refresh your session. You signed out in another tab or window. Reload to refresh your session.