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Learn more - CREATE AN ACCOUNTSIGN IN JOIN IEEESIGN IN Close Access Thousands of Articles -- Completely Free Create an account and get exclusive content and features: Save articles, download collections, and talk to tech insiders -- all free! For full access and benefits, join IEEE as a paying member. CREATE AN ACCOUNTSIGN IN SemiconductorsTopicTypeComputingNews Intel's Take on the Next Wave of Moore's Law Ann B. Kelleher explains what's new 75 years after the transistor's invention Samuel K. Moore 05 Dec 2022 4 min read image of a black and gold computer chip against a black background Intel's Ponte Vecchio processor Intel transistor scaling75th anniversary of the transistorchiplets3D integrationIntelstcodtcoMoore's Law The next wave of Moore's Law will rely on a developing concept called system technology co-optimization, Ann B. Kelleher, general manager of technology development at Intel told IEEE Spectrum in an interview ahead of her plenary talk at the 2022 IEEE Electron Device Meeting. "Moore's Law is about increasing the integration of functions," says Kelleher. "As we look forward into the next 10 to 20 years, there's a pipeline full of innovation" that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference. --------------------------------------------------------------------- Kelleher calls it an "outside-in" manner of development. It starts with the workload a product needs to support and its software, then works down to system architecture, then what type of silicon must be within a package, and finally down to the semiconductor manufacturing process. "With system technology co-optimization, it means all the pieces are optimized together so that you're getting your best answer for the end product," she says. portrait of a woman in a black shirt against a light backgroundAnn B. KelleherIntel STCO is an option now in large part because advanced packaging, such as 3D integration, is allowing the high-bandwidth connection of chiplets--small, functional chips--inside a single package. This means that what would once be functions on a single chip can be disaggregated onto dedicated chiplets, which can each then be made using the most optimal semiconductor process technology. For example, Kelleher points out in her plenary that high-performance computing demands a large amount of cache memory per processor core, but chipmaker's ability to shrink SRAM is not proceeding at the same pace as the scaling down of logic. So it makes sense to build SRAM caches and compute cores as separate chiplets using different process technology and then stitch them together using 3D integration. A key example of STCO in action, says Kelleher, is the Ponte Vecchio processor at the heart of the Aurora supercomputer. It's composed of 47 active chiplets (as well as 8 blanks for thermal conduction). These are stitched together using both advanced horizontal connections (2.5 packaging tech) and 3D stacking. "It brings together silicon from different fabs and enables them to come together so that the system is able to perform against the workload that it's designed for," she says. A chart with a line curving up and to the right, which is overlayed by four bars. Each bar has an image.Intel sees a concept called system technology cooptimizaiton as the next phase of Moore's Law. Intel At IEDM, Intel engineers will report that they've increased the density of their 3D hybrid bonding technology ten-fold versus what they reported in 2021. Increased connection density means more chip functions can be disaggregated onto separate chiplets, in turn providing more potential to use STCO to improve outcomes. Hybrid bond pitches, meaning the distance between the interconnects, are just 3 micrometers with this new technology. With that, even more cache can be separated from the processor cores. Reducing the bond pitch to between 2 micrometers and 100 nanometers could mean being able to start pulling apart logic functions that today must be on the same piece of silicon, according to Kelleher. The drive to optimize systems by disaggregating functions is having consequences for future semiconductor manufacturing processes. Future semiconductor process technology has to contend with the thermal stresses of a 3D-packaged environment. But interconnect technology will probably see the biggest change. Kelleher says Intel is on track to introduce a technology it calls PowerVia (backside power delivery, more generally) in 2024. PowerVia moves a chip's power delivery network beneath the silicon, reducing the size of logic cells and cutting power consumption. But it also "gives us different opportunities in terms of what we can and how we can interconnect in the package," says Kelleher. An illustration of a microchip at left and a bar chart at right. System-technology-cooptimization (STCO) optimizes more of a computer system by taking everything into account from software to process technology.Intel Kelleher stresses that STCO is still in its infancy. Electronic design automation (EDA) tools have already tackled STCO's predecessor, design technology co-optimization (DTCO), which focuses on logic-cell level and functional-block level optimizations. "But some of the EDA tool vendors are already working on this," she says. "Going forward, the focus is going to be on the methods and tools that help enable STCO." As STCO develops, device engineers may have to develop with it. "Generally, engineers will need to continue to have their device knowledge but also begin to understand the use cases of their technology and their devices," says Kelleher. "More interdisciplinary skills will be required as we head into more of an STCO world." Intel's Roadmap Kelleher also updated Intel's roadmap, tying it in with the progression of Moore's Law and the evolution of the device since the invention of the first transistor. The bottom line is that things are on track from when Intel announced its new manufacturing roadmap less than two years ago, according to Kelleher. But she did fill in some details of which processors would debut with the new tech. Five labelled blue bars with writing and cartoons of different microchips on each.Intel is on schedule with its process technology roadmap.Intel Intel 20A, due for manufacturing introduction in the first half of 2024, remains the big technological jump. It simultaneously introduces a new transistor architecture--RibbonFET (more generally called gate-all-around or nanosheet transistors)--and PowerVia backside power delivery. Asked about the risk involved, Kelleher explained the strategy. "They do not have to be done at once, but we see significant benefits from moving to PowerVia to enable the [RibbonFET] technology," she says. The development is happening in parallel to reduce the risk of delays, she explains. Intel is running a test process using FinFETs, the transistor architecture in use today, with PowerVia. "That has been working very successfully and it has enabled us to accelerate our development work," she says. The Transistor of the Future Kelleher's talk comes as the IEEE Electron Device Society celebrates the 75th anniversary of the invention of the transistor. At IEEE Spectrum, we asked experts what the transistor might be like on its 100th birthday in 2047. Kelleher's take took in the long-lifetimes of transistor technology, noting that the planar transistor design lasted from 1960 to about 2010, and that its successor the FinFET is still going strong. "Now we're going to the RibbonFET which is going to last for probably another 20-plus years... so I expect we're going to be somewhere with stacked RibbonFETs," she suggested. [Intel engineers describe that technology in the December 2022 issue of IEEE Spectrum.] However, by that time, the ribbons may be made of 2D semiconductors instead of silicon. From Your Site Articles * Gordon Moore's Next Act > * Next-Gen Chips Will Be Powered From Below > Related Articles Around the Web * Is Moore's Law Slowing Down? What's Next? | IEEE Journals ... > * What's Next? [The end of Moore's law] | IEEE Journals & Magazine ... > transistor scaling75th anniversary of the transistorchiplets3D integrationIntelstcodtcoMoore's Law {"imageShortcodeIds":[]} Samuel K. Moore Samuel K. Moore is the senior editor at IEEE Spectrum in charge of semiconductors coverage. An IEEE member, he has a bachelor's degree in biomedical engineering from Brown University and a master's degree in journalism from New York University. The Conversation (0) different colored beams of light shooting up Artificial IntelligenceTopicTypeComputingNews Deep Learning Gets a Boost From New Reconfigurable Processor 6h 2 min read portrait of a man in a navy blue polo with greenery in the background The InstituteTopicTypeCareersProfile Rory Cooper's Wheelchair Tech Makes the World More Accessible 05 Dec 2022 6 min read Illuminated electric vehicle charging stations at night in Monterey Park, California. TransportationTopicEnergyTypeSpectrum CollectionsAnalysis The EV Transition Explained: Charger Infrastructure 04 Dec 2022 8 min read Related Stories History of TechnologyTopicTypeSemiconductorsGuest ArticleSpecial Reports The Future of the Transistor Is Our Future SemiconductorsTopicDecember 2022MagazineTypeFeatureSpecial Reports The Transistor at 75 SemiconductorsTopicDecember 2022MagazineTypeFeatureHistory of TechnologySpecial Reports The Ultimate Transistor Timeline SemiconductorsTopicDecember 2022MagazineTypeFeatureSpecial Reports The State of the Transistor in 3 Charts In 75 years, it's become tiny, mighty, ubiquitous, and just plain weird Samuel K. Moore David Schneider 26 Nov 2022 4 min read A photo of 3 different transistors. iStockphoto LightGreen The most obvious change in transistor technology in the last 75 years has been just how many we can make. Reducing the size of the device has been a titanic effort and a fantastically successful one, as these charts show. But size isn't the only feature engineers have been improving. This article is part of our special report on the 75th anniversary of the invention of the transistor. In 1947, there was only one transistor. According to TechInsight's forecast, the semiconductor industry is on track to produce almost 2 billion trillion (1021) devices this year. That's more transistors than were cumulatively made in all the years prior to 2017. Behind that barely conceivable number is the continued reduction in the price of a transistor, as engineers have learned to integrate more and more of them into the same area of silicon. Scaling down transistors in the 2D space of the plane of the silicon has been a smashing success: Transistor density in logic circuits has increased more than 600,000-fold since 1971. Reducing transistor size requires using shorter wavelengths of light, such as extreme ultraviolet, and other lithography tricks to shrink the space between transistor gates and between metal interconnects. Going forward, it's the third dimension, where transistors will be built atop one another, that counts. This trend is more than a decade old in flash memory, but it's still in the future for logic (see "Taking Moore's Law to New Heights.") Perhaps the crowning achievement of all this effort is the ability to integrate millions, even billions, of transistors into some of the most complex systems on the planet: CPUs. Here's a look at some of the high points along the way. What Transistors Have Become Besides making them tiny and numerous, engineers have devoted their efforts to enhancing the device's other qualities. Here is a small sampling of what transistors have become in the last 75 years: Icon of a series of circles. Ephemeral: Researchers in Illinois developed circuits that dissolve in the body using a combination of ultrathin silicon membranes, magnesium conductors, and magnesium oxide insulators. Five minutes in water was enough to turn the first generation to mush. But recently researchers used a more durable version to make temporary cardiac pacemakers that release an anti-inflammatory drug as they disappear. An icon of lightning bolt over a circle. Fast: The first transistor was made for radio frequencies, but there are now devices that operate at about a billion times those frequencies. Engineers in South Korea and Japan reported the invention of an indium gallium arsenide high-electron mobility transistor, or HEMT, that reached a maximum frequency of 738 gigahertz. Seeking raw speed, engineers at Northrop Grumman made a HEMT that passed 1 terahertz. An icon of an iron with a line underneath. Flat: Today's (and yesterday's) transistors depend on the semiconducting properties of bulk (3D) materials. Tomorrow's devices might rely on 2D semiconductors, such as molybdenum disulfide and tungsten disulfide. These transistors might be built in the interconnect layers above a processor's silicon, researchers say. So 2D semiconductors could help lead to 3D processors. An icon of a circle with a series of lines on it Flexible: The world is not flat, and neither are the places transistors need to operate. Using indium gallium arsenide, engineers in South Korea recently made high-performance logic transistors on plastic that hardly suffered when bent around a radius of just 4 millimeters. And engineers in Illinois and England have made microcontrollers that are both affordable and bendable. Icon of a eye with a question mark in the center. Invisible: When you need to hide your computing in plain sight, turn to transparent transistors. Researchers in Fuzhou, China, recently made a see-through analogue of flash memory using organic semiconductor thin-film transistors. And researchers in Japan and Malaysia produced transparent diamond devices capable of handling more than 1,000 volts. Icon of a brain made out of square icons Mnemonic: NAND flash memory cells can store multiple bits in a single device. Those on the market today store either 3 or 4 bits each. Researchers at Kioxia Corp. built a modified NAND flash cell and dunked it in 77-kelvin liquid nitrogen. A single superchilled transistor could store up to 7 bits of data, or 128 different values. Icon of a circle with a star inside. Talented: In 2018, engineers in Canada used an algorithm to generate all the possible unique and functional elementary circuits that can be made using just two metal-oxide field-effect transistors. The number of circuits totaled an astounding 582. Increasing the scope to three transistors netted 56,280 circuits, including several amplifiers previously unknown to engineering. Icon of a shield Tough: Some transistors can take otherworldly punishment. NASA Glenn Research Center built 200-transistor silicon carbide ICs and operated them for 60 days in a chamber that simulates the environment on the surface of Venus--460 degC heat, a planetary-probe-crushing 9.3 megapascals of pressure, and the hellish planet's corrosive atmosphere. This article appears in the December 2022 print issue as "The State of the Transistor." [svg] The Transistor at 75 The Transistor at 75 The past, present, and future of the modern world's most important invention How the First Transistor Worked Even its inventors didn't fully understand the point-contact transistor The Ultimate Transistor Timeline The transistor's amazing evolution from point contacts to quantum tunnels The State of the Transistor in 3 Charts In 75 years, it's become tiny, mighty, ubiquitous, and just plain weird 3D-Stacked CMOS Takes Moore's Law to New Heights When transistors can't get any smaller, the only direction is up The Transistor of 2047: Expert Predictions What will the device be like on its 100th anniversary? The Future of the Transistor Is Our Future Nothing but better devices can tackle humanity's growing challenges John Bardeen's Terrific Transistorized Music Box This simple gadget showed off the magic of the first transistor From Your Site Articles * DRAM's Moore's Law Is Still Going Strong > * Intel Now Packs 100 Million Transistors in Each Square Millimeter > * The Nanosheet Transistor Is the Next (and Maybe Last) Step in Moore's Law > * The Transistor at 75 - IEEE Spectrum > Related Articles Around the Web * Transistor count - Wikipedia > * Moore's law - Wikipedia > Keep Reading |Show less {"imageShortcodeIds":[]}