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How close is RISC-V to RISC-I?

Posted on June 19, 2017 by David Patterson
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As part of the celebration of the 50th anniversary of IEEE Computer
 magazine (see below), I've been asked to write a retrospective on "A
VLSI RISC," that was published originally in 1982. (The retrospective
appeared December 2017.)

It's an interesting experience to (re)learn from a paper that you
wrote 35 years ago. For example, which computer first had a register
hardwired to zero? (The answer: the 1951 Ferranti-Manchester MADM,
which was the first machine with index registers, also used a
register to supply zero.)

By far the biggest surprise was how close is the original instruction
set of the RISC-I to the base instruction set of RISC-V (RV32I). The
figure below compares the two instruction sets.  In fact, RISC-I is
may be the closest instruction set to RISC-V of any era; it is
certainly much closer than the original Stanford MIPS and IBM 801
instruction sets.

While architects talk about the differences (register windows,
condition codes, delayed branch),  it's amazing that there aren't
more after 30 years of innovation in computer architecture fueled by
Moore's Law and Dennard Scaling (1981 to 2011). Common features of
RISC-I and RV32I:

  * A 32-bit byte-addressable address space
  * All instructions are 32-bit long
  * 31 registers, with register 0 hardwired to zero, all 32 bits wide
  * All operations are register-to-register (none are
    register-to-memory)
  * The same arithmetic, logical, and shift operations
  * The same load word and store word instructions
  * Signed and unsigned versions of load and store byte and halfword
    (called "short" in RISC-I)
  * Immediate option for all arithmetic, logical, and shift
    instructions
  * Immediates are always sign-extended
  * One data addressing mode (register + immediate)
  * PC-relative branch addressing
  * No multiply or divide instructions
  * An instruction to load a wide immediate into the upper part of
    register so that a 32-bit constant takes only two instructions

Below is the complete ISA for both architectures, aligned by
operation.

[RISC-IvRISC-VB]

Equivalent RISC-V and RISC-I instructions. For RISC-I, "S2" can be
either a 13-bit sign-extended immediate or a second source register.

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