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[gh repo clone corsix] Work fast with our official CLI. Learn more. * Open with GitHub Desktop * Download ZIP Launching GitHub Desktop If nothing happens, download GitHub Desktop and try again. Launching GitHub Desktop If nothing happens, download GitHub Desktop and try again. Launching Xcode If nothing happens, download Xcode and try again. Launching Visual Studio Code Your codespace will open once ready. There was a problem preparing your codespace, please try again. Latest commit @corsix corsix Add XNOR-Net link to matint.md ... 29a9256 Sep 5, 2022 Add XNOR-Net link to matint.md 29a9256 Git stats * 8 commits Files Permalink Failed to load latest commit information. Type Name Latest commit message Commit time .gitignore Initial commit Sep 2, 2022 Instructions.md Fix typo in Instructions.md Sep 3, 2022 LICENSE Initial commit Sep 2, 2022 Makefile Initial commit Sep 2, 2022 README.md Initial commit Sep 2, 2022 References.md Initial commit Sep 2, 2022 RegisterFile.md Add some mixed-lane and shuffle remarks to RegisterFile.md Sep 4, 2022 aarch64.h Initial commit Sep 2, 2022 aarch64.md Initial commit Sep 2, 2022 emulate.h Initial commit Sep 2, 2022 extr.c Initial commit Sep 2, 2022 extr_h.md extrv/extrh lane widths make slightly more conceptual sense when spli... Sep 4, 2022 extr_v.md extrv/extrh lane widths make slightly more conceptual sense when spli... Sep 4, 2022 extr_x.md Initial commit Sep 2, 2022 extr_y.md Initial commit Sep 2, 2022 fig2.png Initial commit Sep 2, 2022 fma.c Initial commit Sep 2, 2022 fma.md Initial commit Sep 2, 2022 fms.c Initial commit Sep 2, 2022 fms.md Initial commit Sep 2, 2022 genlut.c Initial commit Sep 2, 2022 genlut.md Initial commit Sep 2, 2022 ldst.c Initial commit Sep 2, 2022 ldst.md Initial commit Sep 2, 2022 mac16.c Initial commit Sep 2, 2022 mac16.md Initial commit Sep 2, 2022 matfp.c Initial commit Sep 2, 2022 matfp.md Initial commit Sep 2, 2022 matint.c Initial commit Sep 2, 2022 matint.md Add XNOR-Net link to matint.md Sep 5, 2022 setclr.md Initial commit Sep 2, 2022 test.c Rework testing of LD/ST instructions Sep 3, 2022 test.md Initial commit Sep 2, 2022 vecfp.c Initial commit Sep 2, 2022 vecfp.md Initial commit Sep 2, 2022 vecint.c Initial commit Sep 2, 2022 vecint.md Initial commit Sep 2, 2022 View code README.md Contemporary M1 / M2 machines from Apple have (at least) four different ways for low-level programmers to perform heavy computations: 1. Standard ARMv8 SIMD/NEON vector instructions on CPU cores (128 bits wide, issue up to four per cycle on Firestorm) 2. Apple's undocumented AMX instructions, issued from CPU, executed on a special accelerator execution unit 3. The Neural Engine (called ANE or NPU) 4. The GPU (e.g. Metal Compute Shaders) This repository is all about the 2^nd of those: Apple's AMX instructions. Note that these instructions are neither documented nor supported by Apple. As a source of potential great confusion, Apple's AMX instructions are completely distinct from Intel's AMX instructions, though both are intended for issuing matrix multiply operations from a CPU. The research was done on an Apple M1 Max (2021). Older or newer chips might have different AMX instructions. Some sources report that the M1 contains version 2 of the AMX instructions, which seems plausible (possibly everything using 7-bit writemasks comes from version 1, and everything using 9-bit writemasks is new in version 2). A good one-image summary of AMX is the following figure from abandoned patent US20180074824A1. Consider a 32x32 grid of compute units, where each unit can perform 16-bit multiply-accumulate, or a 2x2 subgrid of units can perform 32-bit multiply-accumulate, or a 4x4 subgrid can perform 64-bit multiply-accumulate. To feed this grid, there is a pool of X registers each containing 32 16-bit elements (or 16 32-bit elements, or 8 64-bit elements) and a pool of Y registers similarly containing 32 16-bit elements (or 16 32-bit elements, or 8 64-bit elements). A single instruction can perform a full outer product: multiply every element of an X register with every element of a Y register, and accumulate with the Z element in the corresponding position. US20180074824A1 Figure 2 A single row of the 32x32 grid can also be used to perform vector operations (rather than matrix operations) between X and Y^T. In terms of available data types, the general pattern is: * IEEE754 f16 or f32 or f64 (same width for all three fused-multiply-add operands) * IEEE754 f16 multiplicands, accumulating onto f32 * Integer 8-bit or 16-bit multiplicands, accumulating onto 16 or 32 bits (in various signednesses) This repository provides: * A tiny header for accessing AMX instructions (use at your own risk) * A description of the register file * A full description of every instruction * C code matching the behaviour of every instruction (using inline ARMv8 assembly to express certain things) * References for further reading About Apple AMX Instruction Set Resources Readme License MIT license Stars 247 stars Watchers 10 watching Forks 8 forks Releases No releases published Packages 0 No packages published Contributors 2 * @corsix corsix Peter Cawley * @pthariensflame pthariensflame Alexander Ronald Altman Languages * C 99.5% * Makefile 0.5% Footer (c) 2022 GitHub, Inc. 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