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Learn more - CREATE AN ACCOUNTSIGN IN JOIN IEEESIGN IN Enjoy more free content and benefits by creating an account Create an account to access more content and features on IEEE Spectrum, including the ability to save articles to read later, download Spectrum Collections, and participate in conversations with readers and editors. For more exclusive content and features, consider Joining IEEE. CREATE AN ACCOUNTSIGN IN Type Feature Topic Semiconductors Magazine Next-Gen Chips Will Be Powered From Below Buried interconnects will help save Moore's Law Brian Cline Divya Prasad Eric Beyne Odysseas Zografos 26 Aug 2021 9 min read Horizontal Image of data and power processors functions graphic with a dark background. Chris Philpot DarkGray For a time, each new processor churned out more waste heat than the last. Had these chips kept on the trajectory they were following in the early 2000s, they would soon have packed about 6,400 watts onto each square centimeter--the power flux on the surface of the sun. Things never got that bad because engineers worked to hold down chip power consumption. Data-center system-on-chip (SoC) designs are consistently second only to supercomputer processors in terms of performance, yet they typically consume only about 200 to 400 watts per square centimeter. The chip encased inside that smartphone in your pocket typically draws around 5 W. Nevertheless, while computer chips won't burn a literal hole in your pocket (though they do get hot enough to fry an egg), they still require a lot of current to run the applications we use every day. Consider the data-center SoC: On average, it's consuming 200 W to provide its transistors with about 1 to 2 volts, which means the chip is drawing 100 to 200 amperes of current from the voltage regulators that supply it. Your typical refrigerator draws only 6 A. High-end mobile phones can draw a tenth as much power as data-center SoCs, but even so that's still about 10-20 A of current. That's up to three refrigerators, in your pocket! Delivering that current to billions of transistors is quickly becoming one of the major bottlenecks in high-performance SoC design. As transistors continue to be made tinier, the interconnects that supply them with current must be packed ever closer and be made ever finer, which increases resistance and saps power. This can't go on: Without a big change in the way electrons get to and from devices on a chip, it won't matter how much smaller we can make transistors. Image of data and power processors functions graphic. In today's processors both signals and power reach the silicon [light gray] from above. New technology would separate those functions, saving power and making more room for signal routes [right].Chris Philpot Fortunately, we have a promising solution: We can use a side of the silicon that's long been ignored. Electrons have to travel a long way to get from the source that is generating them to the transistors that compute with them. In most electronics they travel along the copper traces of a printed circuit board into a package that holds the SoC, through the solder balls that connect the chip to the package, and then via on-chip interconnects to the transistors themselves. It's this last stage that really matters. To see why, it helps to understand how chips are made. An SoC starts as a bare piece of high-quality, crystalline silicon. We first make a layer of transistors at the very top of that silicon. Next we link them together with metal interconnects to form circuits with useful computing functions. These interconnects are formed in layers called a stack, and it can take a 10-to-20-layer stack to deliver power and data to the billions of transistors on today's chips. Those layers closest to the silicon transistors are thin and small in order to connect to the tiny transistors, but they grow in size as you go up in the stack to higher levels. It's these levels with broader interconnects that are better at delivering power because they have less resistance. Graphic of power and data transistors from a network above the silicon. Today, both power and signals reach transistors from a network of interconnects above the silicon (the "front side"). But increasing resistance as these interconnects are scaled down to ever-finer dimensions is making that scheme untenable.Chris Philpot You can see, then, that the metal that powers circuits--the power delivery network (PDN)--is on top of the transistors. We refer to this as front-side power delivery. You can also see that the power network unavoidably competes for space with the network of wires that delivers signals, because they share the same set of copper resources. In order to get power and signals off of the SoC, we typically connect the uppermost layer of metal--farthest away from the transistors--to solder balls (also called bumps) in the chip package. So for electrons to reach any transistor to do useful work, they have to traverse 10 to 20 layers of increasingly narrow and tortuous metal until they can finally squeeze through to the very last layer of local wires. This way of distributing power is fundamentally lossy. At every stage along the path, some power is lost, and some must be used to control the delivery itself. In today's SoCs, designers typically have a budget that allows loss that leads to a 10 percent reduction in voltage between the package and the transistors. Thus, if we hit a total efficiency of 90 percent or greater in a power-delivery network, our designs are on the right track. Historically, such efficiencies have been achievable with good engineering--some might even say it was easy compared to the challenges we face today. In today's electronics, SoC designers not only have to manage increasing power densities but to do so with interconnects that are losing power at a sharply accelerating rate with each new generation. You can design a back-side power delivery network that's up to seven times as efficient as the traditional front-side network. The increasing lossiness has to do with how we make nanoscale wires. That process and its accompanying materials trace back to about 1997, when IBM began to make interconnects out of copper instead of aluminum, and the industry shifted along with it. Up until then aluminum wires had been fine conductors, but in a few more steps along the Moore's Law curve their resistance would soon be too high and become unreliable. Copper is more conductive at modern IC scales. But even copper's resistance began to be problematic once interconnect widths shrank below 100 nanometers. Today, the smallest manufactured interconnects are about 20 nm, so resistance is now an urgent issue. It helps to picture the electrons in an interconnect as a full set of balls on a billiards table. Now imagine shoving them all from one end of the table toward another. A few would collide and bounce against each other on the way, but most would make the journey in a straight-ish line. Now consider shrinking the table by half--you'd get a lot more collisions and the balls would move more slowly. Next, shrink it again and increase the number of billiard balls tenfold, and you're in something like the situation chipmakers face now. Real electrons don't collide, necessarily, but they get close enough to one another to impose a scattering force that disrupts the flow through the wire. At nanoscale dimensions, this leads to vastly higher resistance in the wires, which induces significant power-delivery loss. Increasing electrical resistance is not a new challenge, but the magnitude of increase that we are seeing now with each subsequent process node is unprecedented. Furthermore, traditional ways of managing this increase are no longer an option, because the manufacturing rules at the nanoscale impose so many constraints. Gone are the days when we could arbitrarily increase the widths of certain wires in order to combat increasing resistance. Now designers have to stick to certain specified wire widths or else the chip may not be manufacturable. So, the industry is faced with the twin problems of higher resistance in interconnects and less room for them on the chip. There is another way: We can exploit the "empty" silicon that lies below the transistors. At Imec, where authors Beyne and Zografos work, we have pioneered a manufacturing concept called "buried power rails," or BPR. The technique builds power connections below the transistors instead of above them, with the aim of creating fatter, less resistant rails and freeing space for signal-carrying interconnects above the transistor layer. Image of transistors tapping power rails buried within the silicon. To reduce the resistance in power delivery, transistors will tap power rails buried within the silicon. These are relatively large, low-resistance conductors that multiple logic cells could connect with.Chris Philpot To build BPRs, you first have to dig out deep trenches below the transistors and then fill them with metal. You have to do this before you make the transistors themselves. So the metal choice is important. That metal will need to withstand the processing steps used to make high-quality transistors, which can reach about 1,000 degC. At that temperature, copper is molten, and melted copper could contaminate the whole chip. We've therefore experimented with ruthenium and tungsten, which have higher melting points. Since there is so much unused space below the transistors, you can make the BPR trenches wide and deep, which is perfect for delivering power. Compared to the thin metal layers directly on top of the transistors, BPRs can have 1/20 to 1/30 the resistance. That means that BPRs will effectively allow you to deliver more power to the transistors. Furthermore, by moving the power rails off the top side of the transistors you free up room for the signal-carrying interconnects. These interconnects form fundamental circuit "cells"--the smallest circuit units, such as SRAM memory bit cells or simple logic that we use to compose more complex circuits. By using the space we've freed up, we could shrink those cells by 16 percent or more, and that could ultimately translate to more transistors per chip. Even if feature size stayed the same, we'd still push Moore's Law one step further. Unfortunately, it looks like burying local power rails alone won't be enough. You still have to convey power to those rails down from the top side of the chip, and that will cost efficiency and some loss of voltage. Gone are the days when we could arbitrarily increase the widths of certain wires in order to combat increasing resistance. Researchers at Arm, including authors Cline and Prasad, ran a simulation on one of their CPUs and found that, by themselves, BPRs could allow you to build a 40 percent more efficient power network than an ordinary front-side power delivery network. But they also found that even if you used BPRs with front-side power delivery, the overall voltage delivered to the transistors was not high enough to sustain high-performance operation of a CPU. Luckily, Imec was simultaneously developing a complementary solution to further improve power delivery: Move the entire power-delivery network from the front side of the chip to the back side. This solution is called "back-side power delivery," or more generally "back-side metallization." It involves thinning down the silicon that is underneath the transistors to 500 nm or less, at which point you can create nanometer-size "through-silicon vias," or nano-TSVs. These are vertical interconnects that can connect up through the back side of the silicon to the bottom of the buried rails, like hundreds of tiny mineshafts. Once the nano-TSVs have been created below the transistors and BPRs, you can then deposit additional layers of metal on the back side of the chip to form a complete power-delivery network. Expanding on our earlier simulations, we at Arm found that just two layers of thick back-side metal was enough to do the job. As long as you could space the nano-TSVs closer than 2 micrometers from each other, you could design a back-side PDN that was four times as efficient as the front-side PDN with buried power rails and seven times as efficient as the traditional front-side PDN. The back-side PDN has the additional advantage of being physically separated from the signal network, so the two networks no longer compete for the same metal-layer resources. There's more room for each. It also means that the metal layer characteristics no longer need to be a compromise between what power routes prefer (thick and wide for low resistance) and what signal routes prefer (thin and narrow so they can make circuits from densely packed transistors). You can simultaneously tune the back-side metal layers for power routing and the front-side metal layers for signal routing and get the best of both worlds. Image of a power delivery networks on the other side of the silicon, the "back side". Moving the power delivery network to the other side of the silicon--the "back side"--reduces voltage loss even more, because all the interconnects in the network can be made thicker to lower resistance. What's more, removing the power-delivery network from above the silicon leaves more room for signal routes, leading to even smaller logic circuits and letting chipmakers squeeze more transistors into the same area of silicon. Chris Philpot/IMEC In our designs at Arm, we found that for both the traditional front-side PDN and front-side PDN with buried power rails, we had to sacrifice design performance. But with back-side PDN the CPU was able to achieve high frequencies and have electrically efficient power delivery. You might, of course, be wondering how you get signals and power from the package to the chip in such a scheme. The nano-TSVs are the key here, too. They can be used to transfer all input and output signals from the front side to the back side of the chip. That way, both the power and the I/O signals can be attached to solder balls that are placed on the back side. Simulation studies are a great start, and they show the CPU-design-level potential of back-side PDNs with BPR. But there is a long road ahead to bring these technologies to high-volume manufacturing. There are still significant materials and manufacturing challenges that need to be solved. The best choice of metal materials for the BPRs and nano-TSVs is critical to manufacturability and electrical efficiency. Also, the high-aspect-ratio (deep but skinny) trenches needed for both BPRs and nano-TSVs are very difficult to make. Reliably etching tightly spaced, deep-but-narrow features in the silicon substrate and filling them with metal is relatively new to chip manufacture and is still something the industry is getting to grips with. Developing manufacturing tools and methods that are reliable and repeatable will be essential to unlocking widespread adoption of nano-TSVs. Furthermore, battery-powered SoCs, like those in your phone and in other power-constrained designs, already have much more sophisticated power-delivery networks than those we've discussed so far. Modern-day power delivery separates chips into multiple power domains that can operate at different voltages or even be turned off altogether to conserve power. (See " A Circuit to Boost Battery Life," IEEE Spectrum, August 2021.) Image of a chart showing data about power and performance versus voltage loss. In tests of multiple designs using three varieties of power delivery, only back-side power with buried power rails [red] provides enough voltage without compromising performance.Chris Philpot Thus, back-side PDNs and BPRs are eventually going to have to do much more than just efficiently deliver electrons. They're going to have to precisely control where electrons go and how many of them get there. Chip designers will not want to take multiple steps backward when it comes to chip-level power design. So we will have to simultaneously optimize design and manufacturing to make sure that BPRs and back-side PDNs are better than--or at least compatible with--the power-saving IC techniques we use today. The future of computing depends upon these new manufacturing techniques. Power consumption is crucial whether you're worrying about the cooling bill for a data center or the number of times you have to charge your smartphone each day. And as we continue to shrink transistors and ICs, delivering power becomes a significant on-chip challenge. BPR and back-side PDNs may well answer that challenge if engineers can overcome the complexities that come with them. This article appears in the September 2021 print issue as "Power From Below." arm back-side power delivery buried power lines imec interconnects moore's law through silicon vias tsv Brian Cline , Divya Prasad , Eric Beyne and Odysseas Zografos The Conversation (0) Glasses sitting on a case The Institute Type Article Topic Consumer Electronics Tiny Lasers Could Finally Bring Us Really Smart AR Glasses 27 Aug 2021 5 min read Cars and SUVs on a highway Type Opinion Topic Transportation The Age of the Car is Gone, that of the SUV has succeeded 27 Aug 2021 3 min read Two people in white cleanroom suits , masks, and gloves stand on raised platforms examining large equipment. Type Analysis Topic Energy Has Fusion Really Had Its "Wright Brothers" Moment? 27 Aug 2021 7 min read Type Article Topic History of Technology Careers 200 Years Ago, Faraday Invented the Electric Motor After Faraday published his results, his mentor accused him of plagiarism Allison Marsh Allison Marsh is a professor at the University of South Carolina and codirector of the university's Ann Johnson Institute for Science, Technology & Society. She combines her interests in engineering, history, and museum objects to write the Past Forward column, which tells the story of technology through historical artifacts. 27 Aug 2021 7 min read 200 Years Ago, Faraday Invented the Electric Motor electric motors induction ring electric transformer dynamo faraday In 1820, the Danish physicist Hans Christian Orsted threw electromagnetic theory into a state of confusion. Natural philosophers of the day believed that electricity and magnetism were two distinct phenomena, but Orsted suggested that the flow of electricity through a wire created a magnetic field around it. The French physicist Andre-Marie Ampere saw a demonstration of Orsted's experiment in which an electric current deflected a magnetic needle, and he then developed a mathematical theory to explain the relationship. English scientist Michael Faraday soon entered the fray, when Richard Phillips, editor of the Annals of Philosophy, asked him to write a historical account of electromagnetism, a field that was only about two years old and clearly in a state of flux. Faraday was an interesting choice for this task, as Nancy Forbes and Basil Mahon recount in their 2014 book Faraday, Maxwell, and the Electromagnetic Field. Born in 1791, he received only a barebones education at church school in his village of Newington, Surrey (now part of South London). At the age of 14 he was apprenticed to a bookbinder. He read many of the books he bound and continued to look for opportunities to learn more. In a fateful turn of events, just as Faraday's apprenticeship was coming to an end in 1812, one of the bookbinder's clients offered Faraday a ticket to Humphry Davy's farewell lecture series at the Royal Institution of Great Britain. Davy, just 13 years older than Faraday, had already made a name for himself as a chemist. He had discovered sodium, potassium, and several compounds and invented the miner's safety lamp. Plus he was a charismatic speaker. Faraday took detailed notes of the lectures and sent a copy to Davy with a request for employment. When a position opened as a chemistry assistant at the Royal Institution, Davy hired Faraday. Images of Faraday and Davy After Faraday [left] failed to acknowledge his mentor, Humphry Davy [right], in an 1821 paper on the electric motor, Davy accused him of plagiarism.LEFT: ULLSTEIN BILD/GETTY IMAGES; RIGHT: BETTMANN/GETTY IMAGES Davy mentored Faraday and taught him the principles of chemistry. Faraday had an insatiable curiosity, and his reputation at the Royal Institution grew. But when Phillips asked Faraday to write the review article for the Annals, he had only dabbled in electromagnetism and was a bit daunted by Ampere's mathematics. At heart, Faraday was an experimentalist, so in order to write a thorough account, he re-created Orsted's experiments and tried to follow Ampere's reasoning. His "Historical Sketch of Electro-Magnetism," published anonymously in the Annals, described the state of the field, the current research questions and experimental apparatus, the theoretical developments, and the major players. (For a good summary of Faraday's article, see Aaron D. Cobb's "Michael Faraday's 'Historical Sketch of Electro-Magnetism' and the Theory-Dependence of Experimentation," in the December 2009 issue of Philosophy of Science.) While reconstructing Orsted's experiments, Faraday was not entirely convinced that electricity acted like a fluid, running through wires just as water runs through pipes. Instead, he thought of electricity as vibrations resulting from tension between conducting materials. These thoughts kept him experimenting. Faraday observed the circular rotation of a wire as it was attracted and repelled by magnetic poles. "Very satisfactory," he wrote in his notebook. On 3 September 1821, Faraday observed the circular rotation of a wire as it was attracted and repelled by magnetic poles. He sketched in his notebook a clockwise rotation around the south pole of the magnet, and the reverse around the north pole. "Very satisfactory," he wrote in his entry on the day's experiment, "but make more sensible apparatus." The next day, he got it right. He took a deep glass vessel, secured a magnet upright in it with some wax, and then filled the vessel with mercury until the magnetic pole was just above the surface. He floated a stiff wire in the mercury and connected the apparatus to a battery. When a current ran through the circuit, it generated a circular magnetic field around the wire. As the current in the wire interacted with the permanent magnet fixed to the bottom of the dish, the wire rotated clockwise. On the other side of the apparatus, the wire was fixed and the magnet was allowed to move freely, which it did in a circle around the wire. For a helpful animation of Faraday's apparatus, see this tutorial created by the National High Magnetic Field Laboratory. And if you'd like to build your own Faraday motor, this video will walk you through it: Although a great proof of concept, Faraday's device was not exactly useful, except as a parlor trick. Soon, people were snatching up pocket-size motors as novelty gifts. Although Faraday's original motor no longer exists, one that he built the following year does; it's in the collections of the Royal Institution and pictured at top. This simple-looking contraption is the earliest example of an electric motor, the first device to turn electrical energy into mechanical motion. The fallout from Faraday's invention Faraday knew the power of quick publication, and in less than a month he wrote an article, "On Some New Electromagnetic Motions and the Theory of Electromagnetism," which was published in the next issue of the Quarterly Journal of Science, Literature, and the Arts. Unfortunately, Faraday did not appreciate the necessity of fully acknowledging others' contributions to the discovery. Within a week of publication, Humphry Davy dealt his mentee a devastating blow by accusing Faraday of plagiarism. Davy had a notoriously sensitive ego. He was also upset that Faraday failed to adequately credit his friend William Hyde Wollaston, who had been studying the problem of rotary motion with currents and magnets for more than a year. Faraday mentions both men in his article, as well as Ampere, Orsted, and some others. But he doesn't credit anyone as a collaborator, influencer, or codiscoverer. Faraday didn't work directly with Davy and Wollaston on their experiments, but he did overhear a conversation between them and understood the direction of their work. Plus it was (and still is) a common practice to credit your adviser in early publications. When Faraday's reputation began to eclipse that of his mentor's, Faraday made several missteps while navigating the cutthroat, time-sensitive world of academic publishing. Faraday fought to clear his name against the charge of plagiarism and mostly succeeded, although his relationship with Davy remained strained. When Faraday was elected a fellow of the Royal Society in 1824, the sole dissenting vote was cast by the society's president, Humphry Davy. Faraday avoided working in the field of electromagnetism for the next few years. Whether that was his own choice or a choice thrust upon him by Davy's assigning him time-consuming duties within the Royal Institution is an open question. One of Faraday's assignments was to salvage the finances of the Royal Institution, which he did by reinvigorating the lecture series and introducing a popular Christmas lecture. Then in 1825 the Royal Society asked him to lead the Committee for the Improvement of Glass for Optical Purposes, an attempt to revive the British glass industry, which had lost ground to French and German lens makers. This was tedious, bureaucratic work that Faraday undertook as a patriotic duty, but the drudgery and relentless failures took a mental toll. Faraday's experiments of 1831 yield the transformer and the dynamo In 1831, two years after Davy's death and after the completion of Faraday's work on the glass committee, he returned to experimenting with electricity, by way of acoustics. He teamed up with Charles Wheatstone to study sound vibrations. Faraday was particularly interested in how sound vibrations could be seen when a violin bow is pulled across a metal plate lightly covered with sand, creating distinct patterns known as Chladni figures. This video shows the phenomenon in action: Resonance Experiment! (Full Version - With Tones) www.youtube.com Faraday looked at nonlinear standing waves that form on liquid surfaces, which are now known as Faraday waves or Faraday ripples. He published his research, "On a peculiar class of acoustical figures; and on certain forms assumed by groups of particles upon vibrating elastic surfaces," in the Royal Society's Philosophical Transactions. Still convinced that electricity was somehow vibratory, Faraday wondered if electric current passing through a conductor could induce a current in an adjacent conductor. This led him to one of his most famous inventions and experiments: the induction ring. On 29 August 1831, Faraday detailed in his notebook his experiment with a specially prepared iron ring. He wrapped one side of the ring with three lengths of insulated copper wire, each about 24 feet (7 meters) long. The other side, he wrapped with about 60 feet (18 meters) of insulated copper wire. (Although he only describes the assembled ring, it likely took him many days to wrap the wire. Modern experimenters who built a replica spent 10 days on it.) He then began charging one side of the ring and looking at the effects on a magnetic needle a short distance away. To his delight, he was able to induce an electric current from one set of wires to the other, thus creating the first electric transformer. Faraday\u2019s 29 August 1831 notebook entry describes his experiment with a wire-bound iron induction ring\u2014the first electric transformer. Faraday's 29 August 1831 notebook entry describes his experiment with a wire-bound iron induction ring--the first electric transformer.HULTON ARCHIVE/GETTY IMAGES Faraday continued experimenting into the fall of 1831, this time with a permanent magnet. He discovered that he could produce a constant current by rotating a copper disk between the two poles of a permanent magnet. This was the first dynamo, and the direct ancestor of truly useful electric motors. Two hundred years after the discovery of the electric motor, Michael Faraday is rightfully remembered for all of his work in electromagnetism, as well as his skills as a chemist, lecturer, and experimentalist. But Faraday's complex relationship with Davy also speaks to the challenges of mentoring (and being mentored), publishing, and holding (or not) personal grudges. It is sometimes said that Faraday was Davy's greatest discovery, which is a little unfair to Davy, a worthy scientist in his own right. When Faraday's reputation began to eclipse that of his mentor's, Faraday made several missteps while navigating the cutthroat, time-sensitive world of academic publishing. But he continued to do his job--and do it well--creating lasting contributions to the Royal Institution. A decade after his first breakthrough in electromagnetism, he surpassed himself with another. Not bad for a self-taught man with a shaky grasp of mathematics. Part of a continuing series looking at photographs of historical artifacts that embrace the boundless potential of technology. An abridged version of this article appears in the September 2021 print issue as "The Electric Motor at 200." From Your Site Articles * May 1888: Tesla Files His Patents for the Electric Motor - IEEE ... > * The Triumph of the Electric Motor - IEEE Spectrum > Related Articles Around the Web * Michael Faraday's electric magnetic rotation apparatus (motor) | The ... > * The Electric Motor - Edison Tech Center > Keep Reading | Show less Type News Topic Robotics Video Friday: Afghan Girls Robotics Team Reaches Safety Your weekly selection of awesome robot videos Evan Ackerman Evan Ackerman is a senior editor at IEEE Spectrum. Since 2007, he has written over 6,000 articles on robotics and technology. He has a degree in Martian geology and is excellent at playing bagpipes. 27 Aug 2021 3 min read Members of the Afghan Girls Robotics Team leaving aircraft in Mexico Photo: Mexico Foreign Ministry video friday Video Friday is your weekly selection of awesome robotics videos, collected by your friends at IEEE Spectrum robotics. We'll also be posting a weekly calendar of upcoming robotics events for the next few months; here's what we have so far (send us your events!): DARPA SubT Finals - September 21-23, 2021 - Louisville, KY, USA WeRobot 2021 - September 23-25, 2021 - [Online Event] IROS 2021 - September 27-1, 2021 - [Online Event] ROSCon 2021 - October 20-21, 2021 - [Online Event] Let us know if you have suggestions for next week, and enjoy today's videos. Five members of an all-girl Afghan robotics team have arrived in Mexico, fleeing an uncertain future at home after the recent collapse of the U.S.-backed government and takeover by the Taliban. [ Reuters ] via [ FIRST Mexico ] Thanks, Fan! As far as autonomous cars are concerned, there's suburban Arizona difficulty, San Francisco difficulty, and then Asia rush hour difficulty. This is a 9:38 long video that is actually worth watching in its entirety because it's a fully autonomous car from AutoX driving through a Shenzhen urban village. Don't miss the astonished pedestrians, the near-miss with a wandering dog, and the comically one-sided human-vehicle interaction on a single lane road. The AutoX Gen5 system has 50 sensors in total, as well as a vehicle control unit of 2200 TOPS computing power. There are 28 cameras capturing a total of 220 million pixels per second, six high-resolution LiDAR offering 15 million points per second, and 4D RADAR with 0.9-degree resolution encompassing a 360-degree view around the vehicle. Using cameras and LiDAR fusion perception blind spot modules, the Gen5 system covers the entire RoboTaxi body with zero blind spots. [ AutoX ] Sometimes, robots do nice things for humans. [ US Soccer ] Body babbling? Body babbling. [ CVUT ] Thanks, Fan! Matias from the Oxford Robotics Institute writes, "This is a demonstration of our safe visual teach and repeat navigation system running on the ANYmal robot in the Corsham mines/former Cold War bunker in the UK. This is part of some testing we've been doing for the DARPA SubT challenge as part of the Cerberus team." [ Oxford Robotics ] Thanks, Matias! We built a robotic chess player with a universal robot UR5e, a 2D camera, and a deep-learning neural network to illustrate what we do at the Mechatronics, Automation, and Control System Lab at the University of Washington. [ MACS Lab ] via [ UW Engineering ] Thanks, Sarah! Autonomous inspection of powerlines with quadrotors is challenging. Flights require persistent perception to keep a close look at the lines. We propose a method that uses event cameras to robustly track powerlines. The performance is evaluated in real-world flights along a powerline. The tracker is able to persistently track the powerlines, with a mean lifetime of the line 10x longer than existing approaches. [ ETHZ ] I could totally do this, I just choose not to. [ Flexiv ] Thanks, Yunfan! Drone Badminton enables people with low vision to play badminton again using a drone as a ball. This has the potential to diversify the physical activity for people with low vision. [ Digital Nature Group ] Even with the batteries installed, the Open Dynamic Robot Initiative's quadruped is still super skinny looking. [ ODRI ] At USC's Center for Advanced Manufacturing, we have developed a space for multidisciplinary human-robot interaction. The Baxter robot collaborates with the user to execute their own customizable tie-dye design. [ USC Viterbi ] I will never understand the impulse that marketing folks have to add bizarre motor noises to robot videos. [ DeepRobotics ] FedEx and Berkshire Grey have teamed up to streamline small package processing. [ FedEx ] ABB robot amalyzing COVID tests in a fully automated, unmanned state, back and forth between the stations Assist in the delivery of specimens between points, 24 hours a day, 24 hours a day, test results of 96 specimens can be completed every 60 minutes, processing more than 1,800 specimens per day. [ ABB ] Thanks, Fan! This is, and I quote, "the best and greatest robot death scene of all time." [ The Black Hole ] Thanks, Mark! Audrow Nash interviews Melonee Wise for the Sense Think Act podcast. [ Sense Think Act ] Tom Galluzzo interviews Andrew Thomaz for the Crazy Hard Robots podcast. [ Crazy Hard Robots ] Keep Reading | Show less Consumer Electronics Webinar Digitally Integrated Electronic Design - Your Key to Digital Transformation Wednesday, 15 September 2021, 11am ET Altium 27 Aug 2021 1 min read Digitally Integrated Electronic Design - Your Key to Digital Transformation As the complexity and demands of electronics continue to increase, companies attempt to keep up by investing in tools to enhance digital continuity across the electronic development process. However, even with these investments, without a digitally integrated solution, the value chain remains isolated and the process disconnected. This webinar will focus on how you can begin integrating your ECAD, MCAD, simulation and PLM products into a unified digital thread that will enable you to: * Standardize processes to ensure consistency and best practices through managed workflows * Reduce unexpected delays by making informed part choices via on-demand supply-chain * Eliminate manual, error-prone practices with automated, company-defined processes * Easily access, communicate, review and share project data with extended team members electronically via a standard web browser. * Fully trace and audit product trails throughout the whole project lifecycle and decision tree history * Develop a full Digital Twin emulation via connection to enterprise systems including simulation and mechanical design through PLM for product verification and QOR prior to production Our goal is for you to walk away with an understanding of how these typically disparate processes can be linked automatically - enabling you to successfully compete and rise to the top in your industry. Come see what Altium and PTC can do to achieve your unique goals, whether you are just getting started or are already on your path to realizing your own Digital Transformation. Speakers: * Linda Mazzitelli, Sr. Enterprise Solution Architect, Altium * Ruediger Scholz, Senior Product Manager, PLM, PTC Keep Reading | Show less Trending Stories The most-read stories on IEEE Spectrum right now Type Hands On Topic Transportation Magazine A DIY E-bike Conversion on the Cheap 20 Aug 2021 4 min read Blueprint of the simple electric bike conversion. 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