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Redcrafter / verilog2factorio

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This project will compile verilog (a hardware description language)
into factorio blueprints.

GPL-3.0 License
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Mar 21, 2021
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Updated samples
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drastically reduced sim errors and added optimization
Apr 24, 2021
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Implemented new Nodes and some other stuff
Mar 22, 2021
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README.md: Fix typo outpus -> outputs (#7)
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Initial commit
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View code
Factorio verilog compiler Install Usage Examples samples/counter.v
6502 CPU from https://github.com/Arlet/verilog-6502/

README.md

 Factorio verilog compiler

This project will compile verilog (a hardware description language)
into factorio blueprints.

 Install

Manually compile yosys (since the last release is quite old) and add
it to your PATH.

Run npm install to install all dependencies.

 Usage

Run npm start ./samples/counter.v with verilog files as parameters

The compiled blueprint will be output on the command line.

The circuit will have inputs and outputs at the top in the order in
which they were written in the code. Clock pulses are required to be
exactly one tick high. (since adding edge detectors would produce a
lot of overhead)

 Examples

 samples/counter.v

module counter(input clk, input rst, input inc, output reg [3:0] cnt);
  always @(posedge clk) begin
    if (rst)
      cnt <= 0;
    else if (inc)
      cnt <= cnt + 1'b1;
  end
endmodule

image

At the top in order clk, rst, inc and cnt.

 6502 CPU from https://github.com/Arlet/verilog-6502/

(Currently not entirely working) image

About

This project will compile verilog (a hardware description language)
into factorio blueprints.

Topics

compiler factorio verilog

Resources

Readme

License

GPL-3.0 License

Releases

No releases published

Packages 0

No packages published

Contributors 3

  * @Redcrafter Redcrafter Luca
  * @justchen1369 justchen1369
  * @jaller94 jaller94 Christian Paul

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  * TypeScript 100.0%

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