https://dougallj.github.io/applecpu/firestorm-int.html Apple M1 Microarchitecture Research by Dougall Johnson Firestorm: Overview | Base Instructions | SIMD and FP Instructions Icestorm: Overview | Base Instructions | SIMD and FP Instructions Firestorm Base Instructions LAT TP Retire Int Mem FP Units (ports) [*] ADC 1 0.333 1 1 - - u1-3 ADC (32-bit) 1 0.333 1 1 - - u1-3 ADC (64-bit) 1 0.333 1 1 - - u1-3 [*] ADCS 1 0.333 1 1 - - u1-3 ADCS (32-bit) 1 0.333 1 1 - - u1-3 ADCS (64-bit) 1 0.333 1 1 - - u1-3 [*] ADD (extend) 2 0.333 1 2 - - 2*u1-6 ADD (sxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (sxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (uxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (uxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (sxth, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (sxth, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (uxth, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (uxth, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (sxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (uxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] ADD 1 0.167 1 1 - - u1-6 ADD (uxtw, 32-bit) 1 0.167 1 1 - - u1-6 ADD (sxtw, 32-bit) 1 0.167 1 1 - - u1-6 ADD (uxtx, 64-bit) 1 0.167 1 1 - - u1-6 ADD (sxtx, 64-bit) 1 0.167 1 1 - - u1-6 ADD (immediate, 32-bit) 1 0.167 1 1 - - u1-6 ADD (immediate, 64-bit) 1 0.167 1 1 - - u1-6 ADD (shifted immediate, 32-bit) 1 0.167 1 1 - - u1-6 ADD (shifted immediate, 64-bit) 1 0.167 1 1 - - u1-6 ADD (register, 32-bit) 1 0.167 1 1 - - u1-6 ADD (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] ADD (shift) 2 0.333 1 2 - - 2*u1-6 ADD (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 ADD (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 ADD (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] ADDS (extend) 2 0.667 1 2 - - 2*u1-3 ADDS (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] ADDS 1 0.333 1 1 - - u1-3 ADDS (uxtw, 32-bit) 1 0.333 1 1 - - u1-3 ADDS (sxtw, 32-bit) 1 0.333 1 1 - - u1-3 ADDS (uxtx, 64-bit) 1 0.333 1 1 - - u1-3 ADDS (sxtx, 64-bit) 1 0.333 1 1 - - u1-3 ADDS (immediate, 32-bit) 1 0.333 1 1 - - u1-3 ADDS (immediate, 64-bit) 1 0.333 1 1 - - u1-3 ADDS (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3 ADDS (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3 ADDS (register, 32-bit) 1 0.333 1 1 - - u1-3 ADDS (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] ADDS (shift) 2 0.667 1 2 - - 2*u1-3 ADDS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 ADDS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 ADR 0.5 1 1 - - u1/2 ADRP 0.5 1 1 - - u1/2 [*] AND 1 0.167 1 1 - - u1-6 AND (immediate, 32-bit) 1 0.167 1 1 - - u1-6 AND (immediate, 64-bit) 1 0.167 1 1 - - u1-6 AND (register, 32-bit) 1 0.167 1 1 - - u1-6 AND (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] AND (shift) 2 0.333 1 2 - - 2*u1-6 AND (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6 AND (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] ADDS 1 0.333 1 1 - - u1-3 ADDS (immediate, 32-bit) 1 0.333 1 1 - - u1-3 ADDS (immediate, 64-bit) 1 0.333 1 1 - - u1-3 [*] ANDS 1 0.333 1 1 - - u1-3 ANDS (register, 32-bit) 1 0.333 1 1 - - u1-3 ANDS (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] ANDS (shift) 2 0.667 1 2 - - 2*u1-3 ANDS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3 ANDS (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] ASR 1 0.167 1 1 - - u1-6 ASR (immediate, 32-bit) 1 0.167 1 1 - - u1-6 ASR (immediate, 64-bit) 1 0.167 1 1 - - u1-6 ASR (register, 32-bit) 1 0.167 1 1 - - u1-6 ASR (register, 64-bit) 1 0.167 1 1 - - u1-6 AXFLAG 1 0.333 1 1 - - u1-3 B 1 1 - - - - B.cc (not taken) 0.5 1 1 - - u1/2 B.cc (taken) 1 1 1 - - u1/2 [*] BFC 1 1 1 1 - - u6 BFC (32-bit) 1 1 1 1 - - u6 BFC (64-bit) 1 1 1 1 - - u6 [*] BFI 1 1 1 1 - - u6 BFI (32-bit) 1 1 1 1 - - u6 BFI (64-bit) 1 1 1 1 - - u6 [*] BFXIL 1 1 1 1 - - u6 BFXIL (32-bit) 1 1 1 1 - - u6 BFXIL (64-bit) 1 1 1 1 - - u6 [*] BIC 1 0.167 1 1 - - u1-6 BIC (register, 32-bit) 1 0.167 1 1 - - u1-6 BIC (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] BIC (shift) 2 0.333 1 2 - - 2*u1-6 BIC (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6 BIC (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] BICS 1 0.333 1 1 - - u1-3 BICS (register, 32-bit) 1 0.333 1 1 - - u1-3 BICS (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] BICS (shift) 2 0.667 1 2 - - 2*u1-3 BICS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3 BICS (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3 BL 1 1 1 - - u1/2 [*] CAS 3 4 - 3 - CAS (32-bit) 3 4 - 3 - CAS (64-bit) 3 4 - 3 - CASA (32-bit) 3 4 - 3 - CASA (64-bit) 3.053 4 - 3 - [*] CASAL 7 4 - 3 - CASAL (32-bit) 7 4 - 3 - CASAL (64-bit) 7 4 - 3 - [*] CASL 7 4 - 3 - CASL (32-bit) 7 4 - 3 - CASL (64-bit) 7 4 - 3 - CASB 3 4 - 3 - CASAB 3 4 - 3 - CASALB 7 4 - 3 - CASLB 7 4 - 3 - CASH 3 4 - 3 - CASAH 3 4 - 3 - CASALH 7 4 - 3 - CASLH 7 4 - 3 - [*] CASP 14 6 - 3 - CASP (32-bit) 14 6 - 3 - CASP (64-bit) 14 6 - 3 - [*] CASPA 14 6 - 3 - CASPA (32-bit) 14 6 - 3 - CASPA (64-bit) 14 6 - 3 - [*] CASPAL 18 6 - 3 - CASPAL (32-bit) 18 6 - 3 - CASPAL (64-bit) 18 6 - 3 - [*] CASPL 18 6 - 3 - CASPL (32-bit) 18 6 - 3 - CASPL (64-bit) 18 6 - 3 - CBNZ (not taken) 0.5 1 1 - - u1/2 CBNZ (taken) 1.01 1 1 - - u1/2 CBZ (not taken) 0.5 1 1 - - u1/2 CBZ (taken) 1 1 1 - - u1/2 [*] CCMN 1 0.333 1 1 - - u1-3 CCMN (immediate, 32-bit) 1 0.333 1 1 - - u1-3 CCMN (immediate, 64-bit) 1 0.333 1 1 - - u1-3 CCMN (register, 32-bit) 1 0.333 1 1 - - u1-3 CCMN (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] CCMP 1 0.333 1 1 - - u1-3 CCMP (immediate, 32-bit) 1 0.333 1 1 - - u1-3 CCMP (immediate, 64-bit) 1 0.333 1 1 - - u1-3 CCMP (register, 32-bit) 1 0.333 1 1 - - u1-3 CCMP (register, 64-bit) 1 0.333 1 1 - - u1-3 CFINV 1 0.333 1 1 - - u1-3 [*] CINC 1 0.333 1 1 - - u1-3 CINC (32-bit) 1 0.333 1 1 - - u1-3 CINC (64-bit) 1 0.333 1 1 - - u1-3 [*] CINV 1 0.333 1 1 - - u1-3 CINV (32-bit) 1 0.333 1 1 - - u1-3 CINV (64-bit) 1 0.333 1 1 - - u1-3 CLREX 4.976 1 - 1 - [*] CLS 1 0.167 1 1 - - u1-6 CLS (32-bit) 1 0.167 1 1 - - u1-6 CLS (64-bit) 1 0.167 1 1 - - u1-6 [*] CLZ 1 0.167 1 1 - - u1-6 CLZ (32-bit) 1 0.167 1 1 - - u1-6 CLZ (64-bit) 1 0.167 1 1 - - u1-6 [*] CMN (extend) 2 0.667 1 2 - - 2*u1-3 CMN (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] CMN 1 0.333 1 1 - - u1-3 CMN (uxtw, 32-bit) 1 0.333 1 1 - - u1-3 CMN (sxtw, 32-bit) 1 0.333 1 1 - - u1-3 CMN (uxtx, 64-bit) 1 0.333 1 1 - - u1-3 CMN (sxtx, 64-bit) 1 0.333 1 1 - - u1-3 CMN (immediate, 32-bit) 1 0.333 1 1 - - u1-3 CMN (immediate, 64-bit) 1 0.333 1 1 - - u1-3 CMN (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3 CMN (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3 CMN (register, 32-bit) 1 0.333 1 1 - - u1-3 CMN (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] CMN (shift) 2 0.667 1 2 - - 2*u1-3 CMN (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMN (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMN (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] CMP (extend) 2 0.667 1 2 - - 2*u1-3 CMP (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] CMP 1 0.333 1 1 - - u1-3 CMP (uxtw, 32-bit) 1 0.333 1 1 - - u1-3 CMP (sxtw, 32-bit) 1 0.333 1 1 - - u1-3 CMP (uxtx, 64-bit) 1 0.333 1 1 - - u1-3 CMP (sxtx, 64-bit) 1 0.333 1 1 - - u1-3 CMP (immediate, 32-bit) 1 0.333 1 1 - - u1-3 CMP (immediate, 64-bit) 1 0.333 1 1 - - u1-3 CMP (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3 CMP (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3 CMP (register, 32-bit) 1 0.333 1 1 - - u1-3 CMP (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] CMP (shift) 2 0.667 1 2 - - 2*u1-3 CMP (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 CMP (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 CMP (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] CNEG 1 0.333 1 1 - - u1-3 CNEG (32-bit) 1 0.333 1 1 - - u1-3 CNEG (64-bit) 1 0.333 1 1 - - u1-3 [*] CRC32 3 1 1 1 - - u6 CRC32B 3 1 1 1 - - u6 CRC32H 3 1 1 1 - - u6 CRC32W 3 1 1 1 - - u6 CRC32X 3 1 1 1 - - u6 CRC32CB 3 1 1 1 - - u6 CRC32CH 3 1 1 1 - - u6 CRC32CW 3 1 1 1 - - u6 CRC32CX 3 1 1 1 - - u6 CSDB 27 4 - 1 - [*] CSEL 1 0.333 1 1 - - u1-3 CSEL (32-bit) 1 0.333 1 1 - - u1-3 CSEL (64-bit) 1 0.333 1 1 - - u1-3 [*] CSET 1 0.333 1 1 - - u1-3 CSET (32-bit) 1 0.333 1 1 - - u1-3 CSET (64-bit) 1 0.333 1 1 - - u1-3 [*] CSETM 1 0.333 1 1 - - u1-3 CSETM (32-bit) 1 0.333 1 1 - - u1-3 CSETM (64-bit) 1 0.333 1 1 - - u1-3 [*] CSINC 1 0.333 1 1 - - u1-3 CSINC (32-bit) 1 0.333 1 1 - - u1-3 CSINC (64-bit) 1 0.333 1 1 - - u1-3 [*] CSINV 1 0.333 1 1 - - u1-3 CSINV (32-bit) 1 0.333 1 1 - - u1-3 CSINV (64-bit) 1 0.333 1 1 - - u1-3 [*] CSNEG 1 0.333 1 1 - - u1-3 CSNEG (32-bit) 1 0.333 1 1 - - u1-3 CSNEG (64-bit) 1 0.333 1 1 - - u1-3 DMB (SY) 2.913 1 - 1 - DMB (ST) 2.904 1 - 1 - DMB (LD) 2.904 1 - 1 - DMB (ISH) 2.913 1 - 1 - DMB (ISHST) 2.913 1 - 1 - DMB (ISHLD) 2.904 1 - 1 - DMB (NSH) 2.904 1 - 1 - DMB (NSHST) 2.904 1 - 1 - DMB (NSHLD) 2.904 1 - 1 - DMB (OSH) 2.904 1 - 1 - DMB (OSHST) 2.913 1 - 1 - DMB (OSHLD) 2.904 1 - 1 - [*] DSB 17 1 - 1 - DSB (SY) 17 1 - 1 - DSB (ST) 17 1 - 1 - DSB (LD) 17 1 - 1 - DSB (ISH) 17 1 - 1 - DSB (ISHST) 17 1 - 1 - DSB (ISHLD) 17 1 - 1 - DSB (NSH) 17 1 - 1 - DSB (NSHST) 17 1 - 1 - DSB (NSHLD) 17 1 - 1 - DSB (OSH) 17 1 - 1 - DSB (OSHST) 17 1 - 1 - DSB (OSHLD) 17 1 - 1 - [*] EON 1 0.167 1 1 - - u1-6 EON (immediate, 32-bit) 1 0.167 1 1 - - u1-6 EON (immediate, 64-bit) 1 0.167 1 1 - - u1-6 [*] EOR 1 0.167 1 1 - - u1-6 EOR (immediate, 32-bit) 1 0.167 1 1 - - u1-6 EOR (immediate, 64-bit) 1 0.167 1 1 - - u1-6 EOR (register, 32-bit) 1 0.167 1 1 - - u1-6 EOR (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] EOR (shift) 2 0.333 1 2 - - 2*u1-6 EOR (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6 EOR (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] EXTR [1;2] 1 2 2 - - u6, u1-6? EXTR (register, 32-bit) [1;2] 1 2 2 - - u6, u1-6? EXTR (register, 64-bit) [1;2] 1 2 2 - - u6, u1-6? ISB (SY) 28 4 - - - - [*] LDNP 0.333 2 - 1 - u8-10 LDNP (32-bit) 0.333 2 - 1 - u8-10 LDNP (64-bit) 0.333 2 - 1 - u8-10 [*] LDP <=4 0.333 2 - 1 - u8-10 LDP (32-bit) <=4 0.333 2 - 1 - u8-10 LDP (64-bit) <=4 0.333 2 - 1 - u8-10 LDP (post-index, 32-bit) 0.396 3 1 1 - LDP (post-index, 64-bit) 0.407 3 1 1 - LDP (pre-index, 32-bit) 0.394 3 1 1 - LDP (pre-index, 64-bit) 0.406 3 1 1 - [*] LDP (signed offset) <=4 0.333 2 - 1 - u8-10 LDP (signed offset, 32-bit) <=4 0.333 2 - 1 - u8-10 LDP (signed offset, 64-bit) <=4 0.333 2 - 1 - u8-10 LDPSW (post-index) 0.393 3 1 1 - LDPSW (pre-index) 0.396 3 1 1 - LDPSW (signed offset) <=4 0.333 2 - 1 - u8-10 [*] LDR <=4 0.333 1 - 1 - u8-10 LDR (32-bit) <=4 0.333 1 - 1 - u8-10 LDR (64-bit) <=4 0.333 1 - 1 - u8-10 [*] LDR (post-index) 0.368 2 1 1 - LDR (post-index, 32-bit) 0.368 2 1 1 - LDR (post-index, 64-bit) 0.368 2 1 1 - LDR (pre-index, 32-bit) 0.366 2 1 1 - LDR (pre-index, 64-bit) 0.368 2 1 1 - [*] LDR (unsigned offset) <=4 0.333 1 - 1 - u8-10 LDR (unsigned offset, 32-bit) <=4 0.333 1 - 1 - u8-10 LDR (unsigned offset, 64-bit) <=4 0.333 1 - 1 - u8-10 [*] LDR (literal) 0.333 1 - 1 - u8-10 LDR (literal, 32-bit) 0.333 1 - 1 - u8-10 LDR (literal, 64-bit) 0.333 1 - 1 - u8-10 [*] LDR (register) <=4 0.333 1 - 1 - u8-10 LDR (register, 32-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, 64-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, uxtw, 32-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, uxtw, 64-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, sxtw, 32-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, sxtw, 64-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, lsl, 32-bit) <=4 0.333 1 - 1 - u8-10 LDR (register, lsl, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRB <=4 0.333 1 - 1 - u8-10 LDRB (post-index) 0.364 2 1 1 - LDRB (pre-index) 0.365 2 1 1 - LDRB (unsigned offset) <=4 0.333 1 - 1 - u8-10 [*] LDRB (register) <=4 0.333 1 - 1 - u8-10 LDRB (register) <=4 0.333 1 - 1 - u8-10 LDRB (register, uxtw) <=4 0.333 1 - 1 - u8-10 LDRB (register, sxtw) <=4 0.333 1 - 1 - u8-10 LDRH <=4 0.333 1 - 1 - u8-10 LDRH (post-index) 0.368 2 1 1 - LDRH (pre-index) 0.366 2 1 1 - LDRH (unsigned offset) <=4 0.333 1 - 1 - u8-10 [*] LDRH (register) <=4 0.333 1 - 1 - u8-10 LDRH (register) <=4 0.333 1 - 1 - u8-10 LDRH (register, uxtw) <=4 0.333 1 - 1 - u8-10 LDRH (register, sxtw) <=4 0.333 1 - 1 - u8-10 LDRH (register, lsl) <=4 0.333 1 - 1 - u8-10 [*] LDRSB <=4 0.333 1 - 1 - u8-10 LDRSB (32-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (64-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (post-index, 32-bit) 0.364 2 1 1 - LDRSB (post-index, 64-bit) 0.365 2 1 1 - LDRSB (pre-index, 32-bit) 0.365 2 1 1 - LDRSB (pre-index, 64-bit) 0.364 2 1 1 - [*] LDRSB (unsigned offset) <=4 0.333 1 - 1 - u8-10 LDRSB (unsigned offset, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (unsigned offset, 64-bit) <=4 0.333 1 - 1 - u8-10 [*] LDRSB (register) <=4 0.333 1 - 1 - u8-10 LDRSB (register, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (register, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (register, uxtw, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (register, uxtw, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (register, sxtw, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSB (register, sxtw, 64-bit) <=4 0.333 1 - 1 - u8-10 [*] LDRSH <=4 0.333 1 - 1 - u8-10 LDRSH (32-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (64-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (post-index, 32-bit) 0.368 2 1 1 - LDRSH (post-index, 64-bit) 0.365 2 1 1 - LDRSH (pre-index, 32-bit) 0.364 2 1 1 - LDRSH (pre-index, 64-bit) 0.367 2 1 1 - [*] LDRSH (unsigned offset) <=4 0.333 1 - 1 - u8-10 LDRSH (unsigned offset, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (unsigned offset, 64-bit) <=4 0.333 1 - 1 - u8-10 [*] LDRSH (register) <=4 0.333 1 - 1 - u8-10 LDRSH (register, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, uxtw, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, uxtw, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, sxtw, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, sxtw, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, lsl, 32-bit) <=4 0.333 1 - 1 - u8-10 LDRSH (register, lsl, 64-bit) <=4 0.333 1 - 1 - u8-10 LDRSW <=4 0.333 1 - 1 - u8-10 LDRSW (post-index) 0.367 2 1 1 - LDRSW (pre-index) 0.366 2 1 1 - LDRSW (unsigned offset) <=4 0.333 1 - 1 - u8-10 LDRSW (literal) 0.333 1 - 1 - u8-10 [*] LDRSW (register) <=4 0.333 1 - 1 - u8-10 LDRSW (register) <=4 0.333 1 - 1 - u8-10 LDRSW (register, uxtw) <=4 0.333 1 - 1 - u8-10 LDRSW (register, sxtw) <=4 0.333 1 - 1 - u8-10 LDRSW (register, lsl) <=4 0.333 1 - 1 - u8-10 [*] LDUR 0.333 1 - 1 - u8-10 LDUR (32-bit) 0.333 1 - 1 - u8-10 LDUR (64-bit) 0.333 1 - 1 - u8-10 LDURB 0.333 1 - 1 - u8-10 LDURH 0.333 1 - 1 - u8-10 [*] LDURSB 0.333 1 - 1 - u8-10 LDURSB (32-bit) 0.333 1 - 1 - u8-10 LDURSB (64-bit) 0.333 1 - 1 - u8-10 [*] LDURSH 0.333 1 - 1 - u8-10 LDURSH (32-bit) 0.333 1 - 1 - u8-10 LDURSH (64-bit) 0.333 1 - 1 - u8-10 LDURSW 0.333 1 - 1 - u8-10 [*] LSL 1 0.167 1 1 - - u1-6 LSL (immediate, 32-bit) 1 0.167 1 1 - - u1-6 LSL (immediate, 64-bit) 1 0.167 1 1 - - u1-6 LSL (register, 32-bit) 1 0.167 1 1 - - u1-6 LSL (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] LSR 1 0.167 1 1 - - u1-6 LSR (immediate, 32-bit) 1 0.167 1 1 - - u1-6 LSR (immediate, 64-bit) 1 0.167 1 1 - - u1-6 LSR (register, 32-bit) 1 0.167 1 1 - - u1-6 LSR (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] MADD [1;3] 1 1 1 - - u6 MADD (32-bit) [1;3] 1 1 1 - - u6 MADD (64-bit) [1;3] 1 1 1 - - u6 [*] MNEG 3 0.5 1 1 - - u5/6 MNEG (32-bit) 3 0.5 1 1 - - u5/6 MNEG (64-bit) 3 0.5 1 1 - - u5/6 MOV (bitmask immediate, 32-bit) 0.125 1 - - - - MOV (bitmask immediate, 64-bit) 0.125 1 - - - - MOV (from sp, 32-bit) 0.167 1 1 - - u1-6 MOV (from sp, 64-bit) 0.125 1 - - - - [*] MOVK 1 0.167 1 1 - - u1-6 MOVK (32-bit) 1 0.167 1 1 - - u1-6 MOVK (64-bit) 1 0.167 1 1 - - u1-6 [*] MOVN 0.125 1 - - - - MOVN (32-bit) 0.125 1 - - - - MOVN (64-bit) 0.125 1 - - - - [*] MOVZ 0.125 1 - - - - MOVZ (32-bit) 0.125 1 - - - - MOVZ (64-bit) 0.125 1 - - - - MRS (CNTFRQ_EL0) 8.501 1 1 - - MRS (CNTPCT_EL0) 1 1 1 - - u1 MRS (CNTVCT_EL0) 1 1 1 - - u1 MRS (DCZID_EL0) 1 1 1 - - u1 MRS (FPCR) 1 1 1 - - u1 MRS (FPSR) 1 1 1 - - u1 MRS (NZCV) 0.5 1 1 - - u1/2 MRS (TPIDRRO_EL0) 1 1 1 - - u1 MRS (TPIDR_EL0) 1 1 1 - - u1 MRS (DIT) 1 1 1 - - u1 MRS (SSBS) 1 1 1 - - u1 MRS (APRR) 1 1 1 - - u1 MSR (DIT) 12 1 - - - - MSR (SSBS) 3 4 - - - - MSR (APRR) 1.014 1 - - - - MSR (FPCR) 11 1 - - - - MSR (FPSR) 12 1 - - - - MSR (TPIDR_EL0) 12 1 - - - - MSR (NZCV) 0.5 1 1 - - u1/2 [*] MSUB [1;3] 1 1 1 - - u6 MSUB (32-bit) [1;3] 1 1 1 - - u6 MSUB (64-bit) [1;3] 1 1 1 - - u6 [*] MUL 3 0.5 1 1 - - u5/6 MUL (32-bit) 3 0.5 1 1 - - u5/6 MUL (64-bit) 3 0.5 1 1 - - u5/6 [*] MVN 1 0.167 1 1 - - u1-6 MVN (register, 32-bit) 1 0.167 1 1 - - u1-6 MVN (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] MVN (shift) 2 0.333 1 2 - - 2*u1-6 MVN (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6 MVN (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] NEG 1 0.167 1 1 - - u1-6 NEG (register, 32-bit) 1 0.167 1 1 - - u1-6 NEG (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] NEG (shift) 2 0.333 1 2 - - 2*u1-6 NEG (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 NEG (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 NEG (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 NEG (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 NEG (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 NEG (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] NEGS 1 0.333 1 1 - - u1-3 NEGS (register, 32-bit) 1 0.333 1 1 - - u1-3 NEGS (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] NEGS (shift) 2 0.667 1 2 - - 2*u1-3 NEGS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 NEGS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 NEGS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 NEGS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 NEGS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 NEGS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] NGC 1 0.333 1 1 - - u1-3 NGC (register, 32-bit) 1 0.333 1 1 - - u1-3 NGC (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] NGCS 1 0.333 1 1 - - u1-3 NGCS (register, 32-bit) 1 0.333 1 1 - - u1-3 NGCS (register, 64-bit) 1 0.333 1 1 - - u1-3 NOP 0.125 1 - - - - [*] ORN 1 0.167 1 1 - - u1-6 ORN (immediate, 32-bit) 1 0.167 1 1 - - u1-6 ORN (immediate, 64-bit) 1 0.167 1 1 - - u1-6 [*] ORR 1 0.167 1 1 - - u1-6 ORR (immediate, 32-bit) 1 0.167 1 1 - - u1-6 ORR (immediate, 64-bit) 1 0.167 1 1 - - u1-6 ORR (register, 32-bit) 1 0.167 1 1 - - u1-6 ORR (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] ORR (shift) 2 0.333 1 2 - - 2*u1-6 ORR (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6 ORR (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6 PRFM (register, PLDL1KEEP) 1.542 1 - 1 - PRFM (register, PLDL1STRM) 1.548 1 - 1 - PRFM (register, PLDL2KEEP) 1.543 1 - 1 - PRFM (register, PLDL2STRM) 1.403 1 - 1 - PRFM (register, PLDL3KEEP) 1.542 1 - 1 - PRFM (register, PLDL3STRM) 1.545 1 - 1 - PRFM (register, PLIL1KEEP) 1.542 1 - 1 - PRFM (register, PLIL1STRM) 1.353 1 - 1 - PRFM (register, PLIL2KEEP) 1.546 1 - 1 - PRFM (register, PLIL2STRM) 1.544 1 - 1 - PRFM (register, PLIL3KEEP) 1.549 1 - 1 - PRFM (register, PLIL3STRM) 1.546 1 - 1 - PRFM (register, PSTL1KEEP) 1.549 1 - 1 - PRFM (register, PSTL1STRM) 1.553 1 - 1 - PRFM (register, PSTL2KEEP) 1.54 1 - 1 - PRFM (register, PSTL2STRM) 1.544 1 - 1 - PRFM (register, PSTL3KEEP) 1.538 1 - 1 - PRFM (register, PSTL3STRM) 1.539 1 - 1 - PSSBB 27 4 - 1 - [*] RBIT 1 0.167 1 1 - - u1-6 RBIT (32-bit) 1 0.167 1 1 - - u1-6 RBIT (64-bit) 1 0.167 1 1 - - u1-6 [*] REV 1 0.167 1 1 - - u1-6 REV (32-bit) 1 0.167 1 1 - - u1-6 REV (64-bit) 1 0.167 1 1 - - u1-6 [*] REV16 1 0.167 1 1 - - u1-6 REV16 (32-bit) 1 0.167 1 1 - - u1-6 REV16 (64-bit) 1 0.167 1 1 - - u1-6 REV32 1 0.167 1 1 - - u1-6 RMIF 1 0.333 1 1 - - u1-3 [*] ROR 1 0.167 1 1 - - u1-6 ROR (immediate, 32-bit) 1 0.167 1 1 - - u1-6 ROR (immediate, 64-bit) 1 0.167 1 1 - - u1-6 ROR (register, 32-bit) 1 0.167 1 1 - - u1-6 ROR (register, 64-bit) 1 0.167 1 1 - - u1-6 SB 27 4 - 1 - [*] SBC 1 0.333 1 1 - - u1-3 SBC (32-bit) 1 0.333 1 1 - - u1-3 SBC (64-bit) 1 0.333 1 1 - - u1-3 [*] SBCS 1 0.333 1 1 - - u1-3 SBCS (32-bit) 1 0.333 1 1 - - u1-3 SBCS (64-bit) 1 0.333 1 1 - - u1-3 [*] SBFIZ 1 0.167 1 1 - - u1-6 SBFIZ (32-bit) 1 0.167 1 1 - - u1-6 SBFIZ (64-bit) 1 0.167 1 1 - - u1-6 [*] SBFX 1 0.167 1 1 - - u1-6 SBFX (32-bit) 1 0.167 1 1 - - u1-6 SBFX (64-bit) 1 0.167 1 1 - - u1-6 SDIV (fast, 32-bit) 7 2 1 1 - - u5 SDIV (slow, 32-bit) 8 2 1 1 - - u5 SDIV (slow, 32-bit) 8 2 1 1 - - u5 SDIV (fast, 64-bit) 7 2 1 1 - - u5 SDIV (medium, 64-bit) 8 2 1 1 - - u5 SDIV (medium, 64-bit) 8 2 1 1 - - u5 SDIV (slow, 64-bit) 9 2 1 1 - - u5 SDIV (slow, 64-bit) 9 2 1 1 - - u5 SETF8 1 0.333 1 1 - - u1-3 SETF16 1 0.333 1 1 - - u1-3 SMADDL [1;3] 1 1 1 - - u6 SMNEGL 3 0.5 1 1 - - u5/6 SMSUBL [1;3] 1 1 1 - - u6 SMULH 3 0.5 1 1 - - u5/6 SMULL 3 0.5 1 1 - - u5/6 SSBB 27 4 - 1 - [*] STADD 3 3 1 2 - STADD (32-bit) 3 3 1 2 - STADD (64-bit) 3 3 1 2 - [*] STADDL 7 3 1 2 - STADDL (32-bit) 7 3 1 2 - STADDL (64-bit) 7 3 1 2 - STADDB 3 3 1 2 - STADDLB 7 3 1 2 - STADDH 3 3 1 2 - STADDLH 7 3 1 2 - [*] STCLR 3 3 1 2 - STCLR (32-bit) 3 3 1 2 - STCLR (64-bit) 3 3 1 2 - [*] STCLRL 7 3 1 2 - STCLRL (32-bit) 7 3 1 2 - STCLRL (64-bit) 7 3 1 2 - STCLRB 3 3 1 2 - STCLRLB 7 3 1 2 - STCLRH 3 3 1 2 - STCLRLH 7 3 1 2 - [*] STEOR 3 3 1 2 - STEOR (32-bit) 3 3 1 2 - STEOR (64-bit) 3 3 1 2 - [*] STEORL 7 3 1 2 - STEORL (32-bit) 7 3 1 2 - STEORL (64-bit) 7 3 1 2 - STEORB 3 3 1 2 - STEORLB 7 3 1 2 - STEORH 3 3 1 2 - STEORLH 7 3 1 2 - STLLRB 1 1 - 1 - STLLRH 1 1 - 1 - STLRB 1 1 - 1 - STLRH 1 1 - 1 - [*] STLXP 38 1 - 50.67 - STLXP (32-bit) 38 1 - 50.67 - STLXP (64-bit) 38 1 - 50.67 - [*] STLXR 38 1 - 50.67 - STLXR (32-bit) 38 1 - 50.67 - STLXR (64-bit) 38 1 - 50.67 - STLXRB 38 1 - 50.67 - STLXRH 38 1 - 50.67 - [*] STNP 0.521 1 - 1 - STNP (32-bit) 0.521 1 - 1 - STNP (64-bit) 0.521 1 - 1 - [*] STP 0.5 1 - 1 - u7/8 STP (32-bit) 0.5 1 - 1 - u7/8 STP (64-bit) 0.5 1 - 1 - u7/8 STP (post-index, 32-bit) 0.51 1 1 1 - STP (post-index, 64-bit) 0.524 1 1 1 - STP (pre-index, 32-bit) 0.51 1 1 1 - STP (pre-index, 64-bit) 0.524 1 1 1 - [*] STP (signed offset) 0.5 1 - 1 - u7/8 STP (signed offset, 32-bit) 0.5 1 - 1 - u7/8 STP (signed offset, 64-bit) 0.5 1 - 1 - u7/8 [*] STR 0.5 1 - 1 - u7/8 STR (32-bit) 0.5 1 - 1 - u7/8 STR (64-bit) 0.5 1 - 1 - u7/8 STR (post-index, 32-bit) 0.5 1 1 1 - u7/8, u1-6? STR (post-index, 64-bit) 0.51 1 1 1 - STR (pre-index, 32-bit) 0.505 1 1 1 - STR (pre-index, 64-bit) 0.51 1 1 1 - [*] STR (unsigned offset) 0.5 1 - 1 - u7/8 STR (unsigned offset, 32-bit) 0.5 1 - 1 - u7/8 STR (unsigned offset, 64-bit) 0.5 1 - 1 - u7/8 [*] STR (register) 0.5 1 - 1 - u7/8 STR (register, 32-bit) 0.5 1 - 1 - u7/8 STR (register, 64-bit) 0.5 1 - 1 - u7/8 STR (register, uxtw, 32-bit) 0.5 1 - 1 - u7/8 STR (register, uxtw, 64-bit) 0.5 1 - 1 - u7/8 STR (register, sxtw, 32-bit) 0.5 1 - 1 - u7/8 STR (register, sxtw, 64-bit) 0.5 1 - 1 - u7/8 STR (register, lsl, 32-bit) 0.5 1 - 1 - u7/8 STR (register, lsl, 64-bit) 0.5 1 - 1 - u7/8 STRB 0.5 1 - 1 - u7/8 STRB (post-index) 0.505 1 1 1 - STRB (pre-index) 0.509 1 1 1 - STRB (unsigned offset) 0.5 1 - 1 - u7/8 [*] STRB (register) 0.5 1 - 1 - u7/8 STRB (register) 0.5 1 - 1 - u7/8 STRB (register, uxtw) 0.5 1 - 1 - u7/8 STRB (register, sxtw) 0.5 1 - 1 - u7/8 STRH 0.5 1 - 1 - u7/8 STRH (post-index) 0.51 1 1 1 - STRH (pre-index) 0.51 1 1 1 - STRH (unsigned offset) 0.5 1 - 1 - u7/8 [*] STRH (register) 0.5 1 - 1 - u7/8 STRH (register) 0.5 1 - 1 - u7/8 STRH (register, uxtw) 0.5 1 - 1 - u7/8 STRH (register, sxtw) 0.5 1 - 1 - u7/8 [*] STUR 0.5 1 - 1 - u7/8 STUR (32-bit) 0.5 1 - 1 - u7/8 STUR (64-bit) 0.5 1 - 1 - u7/8 STURB 0.5 1 - 1 - u7/8 STURH 0.5 1 - 1 - u7/8 STXP (64-bit) 38 1 - 2.96 - [*] STXR 38 1 - 2.94 - STXR (32-bit) 38 1 - 2.94 - STXR (64-bit) 38 1 - 2.94 - STXRB 38 1 - 2.97 - STXRH 38 1 - 2.95 - [*] SUB (extend) 2 0.333 1 2 - - 2*u1-6 SUB (sxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (sxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (uxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (uxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (sxth, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (sxth, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (uxth, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (uxth, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (sxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (uxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] SUB 1 0.167 1 1 - - u1-6 SUB (uxtw, 32-bit) 1 0.167 1 1 - - u1-6 SUB (sxtw, 32-bit) 1 0.167 1 1 - - u1-6 SUB (uxtx, 64-bit) 1 0.167 1 1 - - u1-6 SUB (sxtx, 64-bit) 1 0.167 1 1 - - u1-6 SUB (immediate, 32-bit) 1 0.167 1 1 - - u1-6 SUB (immediate, 64-bit) 1 0.167 1 1 - - u1-6 SUB (shifted immediate, 32-bit) 1 0.167 1 1 - - u1-6 SUB (shifted immediate, 64-bit) 1 0.167 1 1 - - u1-6 SUB (register, 32-bit) 1 0.167 1 1 - - u1-6 SUB (register, 64-bit) 1 0.167 1 1 - - u1-6 [*] SUB (shift) 2 0.333 1 2 - - 2*u1-6 SUB (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6 SUB (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6 SUB (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6 [*] SUBS (extend) 2 0.667 1 2 - - 2*u1-3 SUBS (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] SUBS 1 0.333 1 1 - - u1-3 SUBS (uxtw, 32-bit) 1 0.333 1 1 - - u1-3 SUBS (sxtw, 32-bit) 1 0.333 1 1 - - u1-3 SUBS (uxtx, 64-bit) 1 0.333 1 1 - - u1-3 SUBS (sxtx, 64-bit) 1 0.333 1 1 - - u1-3 SUBS (immediate, 32-bit) 1 0.333 1 1 - - u1-3 SUBS (immediate, 64-bit) 1 0.333 1 1 - - u1-3 SUBS (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3 SUBS (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3 SUBS (register, 32-bit) 1 0.333 1 1 - - u1-3 SUBS (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] SUBS (shift) 2 0.667 1 2 - - 2*u1-3 SUBS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 SUBS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] SWP 3 2 - 2 - SWP (32-bit) 3 2 - 2 - SWP (64-bit) 3 2 - 2 - SWPA (32-bit) 3 2 - 2 - SWPA (64-bit) 3.047 2 - 2 - [*] SWPAL 7 2 - 2 - SWPAL (32-bit) 7 2 - 2 - SWPAL (64-bit) 7 2 - 2 - [*] SWPL 7 2 - 2 - SWPL (32-bit) 7 2 - 2 - SWPL (64-bit) 7 2 - 2 - SWPB 3 2 - 2 - SWPAB 3 2 - 2 - SWPALB 7 2 - 2 - SWPLB 7 2 - 2 - SWPH 3 2 - 2 - SWPAH 3 2 - 2 - SWPALH 7 2 - 2 - SWPLH 7 2 - 2 - [*] SXTB 1 0.167 1 1 - - u1-6 SXTB (32-bit) 1 0.167 1 1 - - u1-6 SXTB (64-bit) 1 0.167 1 1 - - u1-6 [*] SXTH 1 0.167 1 1 - - u1-6 SXTH (32-bit) 1 0.167 1 1 - - u1-6 SXTH (64-bit) 1 0.167 1 1 - - u1-6 SXTW 1 0.167 1 1 - - u1-6 TBNZ (not taken) 0.5 1 1 - - u1/2 TBNZ (taken) 1 1 1 - - u1/2 TBZ (not taken) 0.5 1 1 - - u1/2 TBZ (taken) 1 1 1 - - u1/2 [*] TST 1 0.333 1 1 - - u1-3 TST (immediate, 32-bit) 1 0.333 1 1 - - u1-3 TST (immediate, 64-bit) 1 0.333 1 1 - - u1-3 TST (register, 32-bit) 1 0.333 1 1 - - u1-3 TST (register, 64-bit) 1 0.333 1 1 - - u1-3 [*] TST (shift) 2 0.667 1 2 - - 2*u1-3 TST (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3 TST (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3 TST (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3 TST (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3 TST (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3 TST (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3 [*] UBFIZ 1 0.167 1 1 - - u1-6 UBFIZ (32-bit) 1 0.167 1 1 - - u1-6 UBFIZ (64-bit) 1 0.167 1 1 - - u1-6 [*] UBFX 1 0.167 1 1 - - u1-6 UBFX (32-bit) 1 0.167 1 1 - - u1-6 UBFX (64-bit) 1 0.167 1 1 - - u1-6 UDIV (fast, 32-bit) 7 2 1 1 - - u5 UDIV (slow, 32-bit) 8 2 1 1 - - u5 UDIV (fast, 64-bit) 7 2 1 1 - - u5 UDIV (medium, 64-bit) 8 2 1 1 - - u5 UDIV (slow, 64-bit) 9 2 1 1 - - u5 UMADDL [1;3] 1 1 1 - - u6 UMNEGL 3 0.5 1 1 - - u5/6 UMSUBL [1;3] 1 1 1 - - u6 UMULH 3 0.5 1 1 - - u5/6 UMULL 3 0.5 1 1 - - u5/6 UXTB 1 0.167 1 1 - - u1-6 UXTH 1 0.167 1 1 - - u1-6 XAFLAG 1 0.333 1 1 - - u1-3 YIELD 0.129 1 - - - -