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standardsemiconductor / lion

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Where Lions Roam: RISC-V on the VELDT

hackage.haskell.org/package/lion
BSD-3-Clause License
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Latest commit

@dopamane
dopamane fix typo
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cb48ac1 Mar 3, 2021
fix typo
cb48ac1

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.github/workflows
update readme and haskell CI
Mar 3, 2021
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remove ice40-prim dependency, use System domain
Mar 3, 2021
lion-metric
cleanup
Mar 3, 2021
lion-soc
bump ice40-prim bounds
Mar 3, 2021
src/Lion
cleanup core interface, use pipeline configuration
Mar 2, 2021
.gitignore
add check passing
Feb 19, 2021
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add riscv-formal submodule
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CHANGELOG.md
update changelog
Feb 28, 2021
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Feb 27, 2021
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fix typo
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add check passing
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lion.cabal
bump ice40-prim bounds
Mar 3, 2021
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README.md

 Where Lions Roam: RISC-V on the VELDT

Haskell CI Hackage Hackage Dependencies

Lion is a formally verified, 5-stage pipeline RISC-V core. Lion
targets the VELDT FPGA development board and is written in Haskell
using Clash.

This repository contains four parts:

 1. The Lion library: a pipelined RISC-V core.
 2. lion-formal: formally verify the core using riscv-formal.
 3. lion-soc: a System-on-Chip demonstrating usage of the Lion core
    on the VELDT.
 4. lion-metric: Observe Yosys synthesis metrics on the Lion Core.

 Lion library

 Usage:

 1. Add lion to build depends section of Cabal file
 2. import module in source files import Lion.Core

When connecting the core to memory and peripherals, ensure single
cycle latency.

 Features

 Current Support

Architecture: RV32I (no FENCE, ECALL, EBREAK)

 Future Support

All features will be added in a configurable manner extending the
base RV32I configuration noted above

  * Zicsr, Control and Status Register (CSR) Instructions
  * CSR registers
  * RV32IM
  * Hard IP ALU

About

Where Lions Roam: RISC-V on the VELDT

hackage.haskell.org/package/lion

Topics

haskell clash risc-v veldt

Resources

Readme

License

BSD-3-Clause License

Releases 1

 
v0.1.0.0 Latest
Feb 28, 2021

Languages

  * Haskell 97.5%
  * Assembly 2.5%

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