io.h - vx32 - Local 9vx git repository for patches.
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io.h (9401B)
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1 #define X86STEPPING(x) ((x) & 0x0F)
2 /* incorporate extended-model bits */
3 #define X86MODEL(x) ((((x)>>4) & 0x0F) | (((x)>>16) & 0x0F)<<4)
4 #define X86FAMILY(x) (((x)>>8) & 0x0F)
5
6 enum {
7 VectorNMI = 2, /* non-maskable interrupt */
8 VectorBPT = 3, /* breakpoint */
9 VectorUD = 6, /* invalid opcode exception */
10 VectorCNA = 7, /* coprocessor not available */
11 Vector2F = 8, /* double fault */
12 VectorCSO = 9, /* coprocessor segment overrun */
13 VectorPF = 14, /* page fault */
14 Vector15 = 15, /* reserved */
15 VectorCERR = 16, /* coprocessor error */
16
17 VectorPIC = 32, /* external i8259 interrupts */
18 IrqCLOCK = 0,
19 IrqKBD = 1,
20 IrqUART1 = 3,
21 IrqUART0 = 4,
22 IrqPCMCIA = 5,
23 IrqFLOPPY = 6,
24 IrqLPT = 7,
25 IrqIRQ7 = 7,
26 IrqAUX = 12, /* PS/2 port */
27 IrqIRQ13 = 13, /* coprocessor on 386 */
28 IrqATA0 = 14,
29 IrqATA1 = 15,
30 MaxIrqPIC = 15,
31
32 VectorLAPIC = VectorPIC+16, /* local APIC interrupts */
33 IrqLINT0 = 16, /* LINT[01] must be offsets 0 and 1 */
34 IrqLINT1 = 17,
35 IrqTIMER = 18,
36 IrqERROR = 19,
37 IrqPCINT = 20,
38 IrqSPURIOUS = 31, /* must have bits [3-0] == 0x0F */
39 MaxIrqLAPIC = 31,
40
41 VectorSYSCALL = 64,
42
43 VectorAPIC = 65, /* external APIC interrupts */
44 MaxVectorAPIC = 255,
45 };
46
47 struct Vctl {
48 Vctl* next; /* handlers on this vector */
49
50 char name[KNAMELEN]; /* of driver */
51 int isintr; /* interrupt or fault/trap */
52 int irq;
53 int tbdf;
54 int (*isr)(int); /* get isr bit for this irq */
55 int (*eoi)(int); /* eoi */
56
57 void (*f)(Ureg*, void*); /* handler to call */
58 void* a; /* argument to call it with */
59 };
60
61 enum {
62 BusCBUS = 0, /* Corollary CBUS */
63 BusCBUSII, /* Corollary CBUS II */
64 BusEISA, /* Extended ISA */
65 BusFUTURE, /* IEEE Futurebus */
66 BusINTERN, /* Internal bus */
67 BusISA, /* Industry Standard Architecture */
68 BusMBI, /* Multibus I */
69 BusMBII, /* Multibus II */
70 BusMCA, /* Micro Channel Architecture */
71 BusMPI, /* MPI */
72 BusMPSA, /* MPSA */
73 BusNUBUS, /* Apple Macintosh NuBus */
74 BusPCI, /* Peripheral Component Interconnect */
75 BusPCMCIA, /* PC Memory Card International Association */
76 BusTC, /* DEC TurboChannel */
77 BusVL, /* VESA Local bus */
78 BusVME, /* VMEbus */
79 BusXPRESS, /* Express System Bus */
80 };
81
82 #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
83 #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
84 #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
85 #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
86 #define BUSTYPE(tbdf) ((tbdf)>>24)
87 #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
88 #define BUSUNKNOWN (-1)
89
90 enum {
91 MaxEISA = 16,
92 CfgEISA = 0xC80,
93 };
94
95 /*
96 * PCI support code.
97 */
98 enum { /* type 0 & type 1 pre-defined header */
99 PciVID = 0x00, /* vendor ID */
100 PciDID = 0x02, /* device ID */
101 PciPCR = 0x04, /* command */
102 PciPSR = 0x06, /* status */
103 PciRID = 0x08, /* revision ID */
104 PciCCRp = 0x09, /* programming interface class code */
105 PciCCRu = 0x0A, /* sub-class code */
106 PciCCRb = 0x0B, /* base class code */
107 PciCLS = 0x0C, /* cache line size */
108 PciLTR = 0x0D, /* latency timer */
109 PciHDT = 0x0E, /* header type */
110 PciBST = 0x0F, /* BIST */
111
112 PciBAR0 = 0x10, /* base address */
113 PciBAR1 = 0x14,
114
115 PciINTL = 0x3C, /* interrupt line */
116 PciINTP = 0x3D, /* interrupt pin */
117 };
118
119 /* ccrb (base class code) values; controller types */
120 enum {
121 Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
122 Pcibcstore = 1, /* mass storage */
123 Pcibcnet = 2, /* network */
124 Pcibcdisp = 3, /* display */
125 Pcibcmmedia = 4, /* multimedia */
126 Pcibcmem = 5, /* memory */
127 Pcibcbridge = 6, /* bridge */
128 Pcibccomm = 7, /* simple comms (e.g., serial) */
129 Pcibcbasesys = 8, /* base system */
130 Pcibcinput = 9, /* input */
131 Pcibcdock = 0xa, /* docking stations */
132 Pcibcproc = 0xb, /* processors */
133 Pcibcserial = 0xc, /* serial bus (e.g., USB) */
134 Pcibcwireless = 0xd, /* wireless */
135 Pcibcintell = 0xe, /* intelligent i/o */
136 Pcibcsatcom = 0xf, /* satellite comms */
137 Pcibccrypto = 0x10, /* encryption/decryption */
138 Pcibcdacq = 0x11, /* data acquisition & signal proc. */
139 };
140
141 /* ccru (sub-class code) values; common cases only */
142 enum {
143 /* mass storage */
144 Pciscscsi = 0, /* SCSI */
145 Pciscide = 1, /* IDE (ATA) */
146
147 /* network */
148 Pciscether = 0, /* Ethernet */
149
150 /* display */
151 Pciscvga = 0, /* VGA */
152 Pciscxga = 1, /* XGA */
153 Pcisc3d = 2, /* 3D */
154
155 /* bridges */
156 Pcischostpci = 0, /* host/pci */
157 Pciscpcicpci = 1, /* pci/pci */
158
159 /* simple comms */
160 Pciscserial = 0, /* 16450, etc. */
161 Pciscmultiser = 1, /* multiport serial */
162
163 /* serial bus */
164 Pciscusb = 3, /* USB */
165 };
166
167 enum { /* type 0 pre-defined header */
168 PciCIS = 0x28, /* cardbus CIS pointer */
169 PciSVID = 0x2C, /* subsystem vendor ID */
170 PciSID = 0x2E, /* cardbus CIS pointer */
171 PciEBAR0 = 0x30, /* expansion ROM base address */
172 PciMGNT = 0x3E, /* burst period length */
173 PciMLT = 0x3F, /* maximum latency between bursts */
174 };
175
176 enum { /* type 1 pre-defined header */
177 PciPBN = 0x18, /* primary bus number */
178 PciSBN = 0x19, /* secondary bus number */
179 PciUBN = 0x1A, /* subordinate bus number */
180 PciSLTR = 0x1B, /* secondary latency timer */
181 PciIBR = 0x1C, /* I/O base */
182 PciILR = 0x1D, /* I/O limit */
183 PciSPSR = 0x1E, /* secondary status */
184 PciMBR = 0x20, /* memory base */
185 PciMLR = 0x22, /* memory limit */
186 PciPMBR = 0x24, /* prefetchable memory base */
187 PciPMLR = 0x26, /* prefetchable memory limit */
188 PciPUBR = 0x28, /* prefetchable base upper 32 bits */
189 PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
190 PciIUBR = 0x30, /* I/O base upper 16 bits */
191 PciIULR = 0x32, /* I/O limit upper 16 bits */
192 PciEBAR1 = 0x28, /* expansion ROM base address */
193 PciBCR = 0x3E, /* bridge control register */
194 };
195
196 enum { /* type 2 pre-defined header */
197 PciCBExCA = 0x10,
198 PciCBSPSR = 0x16,
199 PciCBPBN = 0x18, /* primary bus number */
200 PciCBSBN = 0x19, /* secondary bus number */
201 PciCBUBN = 0x1A, /* subordinate bus number */
202 PciCBSLTR = 0x1B, /* secondary latency timer */
203 PciCBMBR0 = 0x1C,
204 PciCBMLR0 = 0x20,
205 PciCBMBR1 = 0x24,
206 PciCBMLR1 = 0x28,
207 PciCBIBR0 = 0x2C, /* I/O base */
208 PciCBILR0 = 0x30, /* I/O limit */
209 PciCBIBR1 = 0x34, /* I/O base */
210 PciCBILR1 = 0x38, /* I/O limit */
211 PciCBSVID = 0x40, /* subsystem vendor ID */
212 PciCBSID = 0x42, /* subsystem ID */
213 PciCBLMBAR = 0x44, /* legacy mode base address */
214 };
215
216 typedef struct Pcisiz Pcisiz;
217 struct Pcisiz
218 {
219 Pcidev* dev;
220 int siz;
221 int bar;
222 };
223
224 struct Pcidev
225 {
226 int tbdf; /* type+bus+device+function */
227 ushort vid; /* vendor ID */
228 ushort did; /* device ID */
229
230 ushort pcr;
231
232 uchar rid;
233 uchar ccrp;
234 uchar ccru;
235 uchar ccrb;
236 uchar cls;
237 uchar ltr;
238
239 struct {
240 ulong bar; /* base address */
241 int size;
242 } mem[6];
243
244 struct {
245 ulong bar;
246 int size;
247 } rom;
248 uchar intl; /* interrupt line */
249
250 Pcidev* list;
251 Pcidev* link; /* next device on this bno */
252
253 Pcidev* bridge; /* down a bus */
254 struct {
255 ulong bar;
256 int size;
257 } ioa, mema;
258
259 int pmrb; /* power management register block */
260 };
261
262 #define PCIWINDOW 0
263 #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
264 #define ISAWINDOW 0
265 #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
266
267 /* SMBus transactions */
268 enum
269 {
270 SMBquick, /* sends address only */
271
272 /* write */
273 SMBsend, /* sends address and cmd */
274 SMBbytewrite, /* sends address and cmd and 1 byte */
275 SMBwordwrite, /* sends address and cmd and 2 bytes */
276
277 /* read */
278 SMBrecv, /* sends address, recvs 1 byte */
279 SMBbyteread, /* sends address and cmd, recv's byte */
280 SMBwordread, /* sends address and cmd, recv's 2 bytes */
281 };
282
283 typedef struct SMBus SMBus;
284 struct SMBus {
285 QLock lk; /* mutex */
286 Rendez r; /* rendezvous point for completion interrupts */
287 void *arg; /* implementation dependent */
288 ulong base; /* port or memory base of smbus */
289 int busy;
290 void (*transact)(SMBus*, int, int, int, uchar*);
291 };
292
293 /*
294 * PCMCIA support code.
295 */
296
297 typedef struct PCMconftab PCMconftab;
298
299 /*
300 * Map between ISA memory space and PCMCIA card memory space.
301 */
302 struct PCMmap {
303 ulong ca; /* card address */
304 ulong cea; /* card end address */
305 ulong isa; /* ISA address */
306 int len; /* length of the ISA area */
307 int attr; /* attribute memory */
308 int ref;
309 };
310
311 /* configuration table entry */
312 struct PCMconftab
313 {
314 int index;
315 ushort irqs; /* legal irqs */
316 uchar irqtype;
317 uchar bit16; /* true for 16 bit access */
318 struct {
319 ulong start;
320 ulong len;
321 } io[16];
322 int nio;
323 uchar vpp1;
324 uchar vpp2;
325 uchar memwait;
326 ulong maxwait;
327 ulong readywait;
328 ulong otherwait;
329 };
330
331 /* a card slot */
332 struct PCMslot
333 {
334 Lock lk;
335 int ref;
336
337 void *cp; /* controller for this slot */
338 long memlen; /* memory length */
339 uchar base; /* index register base */
340 uchar slotno; /* slot number */
341
342 /* status */
343 uchar special; /* in use for a special device */
344 uchar already; /* already inited */
345 uchar occupied;
346 uchar battery;
347 uchar wrprot;
348 uchar powered;
349 uchar configed;
350 uchar enabled;
351 uchar busy;
352
353 /* cis info */
354 ulong msec; /* time of last slotinfo call */
355 char verstr[512]; /* version string */
356 int ncfg; /* number of configurations */
357 struct {
358 ushort cpresent; /* config registers present */
359 ulong caddr; /* relative address of config registers */
360 } cfg[8];
361 int nctab; /* number of config table entries */
362 PCMconftab ctab[8];
363 PCMconftab *def; /* default conftab */
364
365 /* memory maps */
366 Lock mlock; /* lock down the maps */
367 int time;
368 PCMmap mmap[4]; /* maps, last is always for the kernel */
369 };
370