# AVR assembler specificities

Load with "AVRA".

All mnemonics in AVR have a single signature. Therefore, we
don't need any "argtype" suffixes.

Registers are referred to with consts R0-R31. There is
X, Y, Z, X+, Y+, Z+, X-, Y-, Z- for appropriate ops (LD, ST).
XL, XH, YL, YH, ZL, ZH are simple aliases to R26-R31.

Branching works differently. Instead of expecting a byte to be
written after the naked op, branching words expect a displace-
ment argument.

This is because there's bitwise ORing involved in the creation
of the final opcode, which makes z80a's approach impractical.

This makes labelling a bit different too. Instead of expecting
label words after the naked branching op, we rather have label
words expecting branching wordref as an argument. Examples:

' BRTS L2 TO, ( branch forward to L2 )
' RJMP L1 LBL, ( branch backward to L1 )

# Model-specific constants

Model-specific constants must be loaded separately. AVRA
supplies loader words. Here's a list:

ATMEGA328P

Those units contain register constants such as PORTB, DDRB, etc.
Unlike many modern assemblers, they do not include bit
constants. Here's an example use:

DDRB 5 SBI,
PORTB 5 CBI,
R16 TIFR0 IN,
R16 0 ( TOV0 ) SBRS,

# Instructions list

OPRd
ASR  COM   DEC   INC   LAC   LAS   LAT   LSR   NEG   POP   PUSH
ROR  SWAP  XCH

OPRdRr
ADC  ADD   AND   CP    CPC   CPSE  EOR   MOV   MUL   OR   SBC
SUB

OPRdA
IN   OUT

OPRdK
ANDI CPI   LDI   ORI   SBCI   SBR   SUBI

OPAb
CBI   SBI   SBIC  SBIS

OPNA
BREAK  CL[C,H,I,N,S,T,V,Z] SE[C,H,I,N,S,T,V,Z] EIJMP ICALL
EICALL IJMP  NOP   RET   RETI  SLEEP WDR

OPb
BCLR  BSET

OPRdb
BLD   BST   SBRC  SBRS

Special
CLR   TST   LSL   LD    ST

Flow
RJMP  RCALL
BR[BC,BS,CC,CS,EQ,NE,GE,HC,HS,ID,IE,LO,LT,MI,PL,SH,TC,TS,VC,VS]

Flow macros
LBL! LBL, SKIP, TO, FLBL, FLBL! BEGIN, AGAIN? AGAIN, IF, THEN,