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, ADL, abstraction, algorithmiclevel, asynchronous, automation, BDD, Benchmarks, CAPRA, circuits, classification of properties, compiler, complexity, concurrent programs, CONLAN, ctl, cve, DDL, Design, ELLA, eventstructure, fair transition system, fairness, finite-state system, firstorderlogic, flowgraph, formal methods, formalism, formalsynthesis, fsm, gatelevel, general, graph, hardware, HDL, higherorderlogic, HOL, HOL-System, itl, KARL, layout, layoutlevel, liveness, Logic, ltl, Methods, microprocessor, ML, modelchecking, modelling, omega, omegafsm, optimization, other, petrinet, processalgebra, program verification, progress, PROLOG, proof systems, propositionallogic, reachability analysis, reactive systems, realtime, recurrence, refinement, registertransferlevel, responsiveness, Rewrite, rewriting, RISC, safety, SFB358, shortest path, SILAGE, simulation, SMAX, SML, software, softwareverification, specification, survey, switchlevel, symbolic state traversal, symbolicsimulation, synthesis, system, systemlevel, techreport, temporallogic, test, textbook, theorem proving, timers, timing, tpcd94, trace, trajectoryevaluation, transistorlevel, transition, transitionsystem, transitionsystemfair, transitionsystemlabelled, transpositionsystem, tutorial, UNITY, verification, verificationformalism, VHDL, VIOLA, voss" />
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<h1 class="page_title">The Collection of<br />Computer Science Bibliographies</h1><ul class="top_nav"><li><a href="../index.html" title="Home page of The Collection of Computer Science Bibliographies">Collection Home</a></li>
<li><a href="index.html">Up: Bibliographies on Software/Hardware Engineering and Formal Methods</a></li>
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<h1 class="subcollectiontitle">Bibliography on Hardware Verification and Formal Methods</h1>
<p style="text-align:center; font-size:small">[ &nbsp; <a href="#about">About</a> &nbsp; | &nbsp;<a href="#browse">Browse</a> &nbsp; | &nbsp; <a href="#stats">Statistics</a> &nbsp; ]</p><table width="100%" cellpadding="0"><colgroup span="4" width="1*" /><tr><th align="right">Number of references:</th><td align="left">2602</td><th align="right">Last update:</th><td align="left">April 28, 2000</td></tr><tr><th align="right">Number of online publications:</th><td align="left">494</td><th align="right">Supported:</th><td align="left">yes</td>
</tr><tr><th align="right">Most recent reference:</th><td align="left">June 1998</td>
<th> </th><td> </td></tr></table>

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<h2 class="h2bar"><a id="about">Information on the Bibliography</a></h2>
<dl>
<dt><strong>Author:</strong></dt>
<dd><a href="http://goethe.ira.uka.de/hvg/">Hardware Verification Group</a><br />
Hardware Verification Group at the Institute of Computer Design and Fault Tolerance<br /> Department of Computer Science<br /> University of Karlsruhe<br /> Germany
</dd><dt><strong>Abstract:</strong></dt><dd>
This is a reference list on hardware verification and formal methods in general.</dd>
<dt><strong>Keywords:</strong></dt><dd>
ADL, abstraction, algorithmiclevel, asynchronous, automation, BDD, Benchmarks, CAPRA, circuits, classification of properties, compiler, complexity, concurrent programs, CONLAN, ctl, cve, DDL, Design, ELLA, eventstructure, fair transition system, fairness, finite-state system, firstorderlogic, flowgraph, formal methods, formalism, formalsynthesis, fsm, gatelevel, general, graph, hardware, HDL, higherorderlogic, HOL, HOL-System, itl, KARL, layout, layoutlevel, liveness, Logic, ltl, Methods, microprocessor, ML, modelchecking, modelling, omega, omegafsm, optimization, other, petrinet, processalgebra, program verification, progress, PROLOG, proof systems, propositionallogic, reachability analysis, reactive systems, realtime, recurrence, refinement, registertransferlevel, responsiveness, Rewrite, rewriting, RISC, safety, SFB358, shortest path, SILAGE, simulation, SMAX, SML, software, softwareverification, specification, survey, switchlevel, symbolic state traversal, symbolicsimulation, synthesis, system, systemlevel, techreport, temporallogic, test, textbook, theorem proving, timers, timing, tpcd94, trace, trajectoryevaluation, transistorlevel, transition, transitionsystem, transitionsystemfair, transitionsystemlabelled, transpositionsystem, tutorial, UNITY, verification, verificationformalism, VHDL, VIOLA, voss</dd>
<dt><strong>Author Comments:</strong></dt><dd>
Feel free to use, copy, alter or redistribute this file, but please include proper acknowledgement.<br /> Realize that it is by no means a complete or exhaustive list. Comments, corrections and additions can be sent to kropf@informatik.uni-karlsruhe.de.</dd>

</dl>
<h2 class="h2bar"><a id="browse">Browsing the bibliography</a></h2>
<ul><li><dl>
<dt><strong>Original source:</strong></dt>
<dd><a href="ftp://goethe.ira.uka.de/pub/hvg/bibliography/literatur.bib.gz">ftp://goethe.ira.uka.de</a>...
(Format: bibtex, compressed with gzip) 
</dd><dt><strong>Other sites:</strong></dt>
<dd><a href="http://goethe.ira.uka.de/hvg/bibliography.html">http://goethe.ira.uka.de</a>...
(searchable index)
(Format: bibtex)
<br />
</dd>
</dl></li></ul>
<h2 class="h2bar"><a id="stats">Bibliographic Statistics</a></h2>
<dl>
<dt><strong>Types:</strong></dt>
<dd>inproceedings(1621), article(417), techreport(195),
book(175), phdthesis(46), incollection(45),
 proceedings(27), inbook(23), manual(18), misc(18),
 mastersthesis(14), unpublished(2), booklet(1)</dd><dt><strong>Fields:</strong></dt>
<dd>year(2602), key(2600), title(2600), author(2549),
pages(1746), booktitle(1668), address(1508),
 publisher(1497), month(1450), keyword(1155),
 editor(1023), volume(914), organization(693),
 series(600), journal(417), number(342),
 institution(187), note(186), school(59), type(44),
 chapter(35), remark(35), edition(24), howpublished(13),
 isbn(10)</dd><dt><strong>Distribution of publication dates:</strong></dt>
<dd style="text-align:center">
<object data="formal.hardware.verification.years.stats.svgz" type="image/svg+xml" width="800" height="400" style="width: 80ex; height: 40ex;">
<img src="formal.hardware.verification.years.stats.png" alt="Distribution of publication dates" title="Distribution of publication dates" />
</object></dd>
</dl>
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