A scratchpad for random thoughts re spudstop.
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ICH2-M and ICH3-M chipsets (mobile Camino 2 and 3) are fully supported
by CPUFreq speedstep.c - a mostly documented interface (a read/write
register in the LPC bridge function of the chipset) allows for
switching and reading state.

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Some notes on the detection whether a Coppermine PIII is SpeedStep
capable:

higher 32 bits of MSR 0x17 (MSR 0x2a doesn't tell us):

         	 	  60 				     32
	 	           x    z zzzy yy                     x
mobile P3 coppermines:
high speed settings:
600 MHz - 0x5a540000 -> 0101 1010 0101 1000 0000 0000 0000 0000
850 MHz - 0x33550000 -> 0011 0011 0101 0101 0000 0000 0000 0000
750 MHz - 0x6b560000 -> 0011 1011 0101 0110 0000 0000 0000 0000
low speed settings:
500 MHz - 0x02540000 -> 0000 0010 0101 1000 0000 0000 0000 0000
700 MHz - 0x4b550000 -> 0100 1011 0101 0101 0000 0000 0000 0000

non-mobile P3 coppermines (first has 100MHz FSB, second 133 MHz)
700 MHz - 0x4a400000 -> 0100 1010 0100 0000 0000 0000 0000 0000
850 MHz - 0x79530000 -> 0111 1001 0101 0011 0000 0000 0000 0000

bit 60 (x)	     : "Clock Frequency Ratio read" (according to 
		       an Intel doc). But what does this mean?
bits 53-56 (z)	     : L2 Cache latency read
bits 50-52 (y)	     : Processor Flag / Platform ID

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On some chipsets, and certain BIOSes, it might be possible to use the
"0xB2 APM interface" reverse engineered by Martin Malik
<martin.malik@siemens.at>. You can find an user-space interface
developed by Marc A. Lehmann <pcg@goof.com> at
http://www.goof.com/pcg/marc/speedstep.html

If you find a chipset / BIOS that works with his implementation but
not the CPUFreq interface, please let me know. (Dominik Brodowski,
<devel@brodo.de>)

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Intel PIIX4 (BX/MX chipsets) support still has to be 
reverse-engineered as Intel continues to withhold the documentation 
for this "1st type of speedstep". Here are some pointers to Intel 
documents.

important(?) documents at developer.intel.com:


27350401.pdf p. 25-27 -- Mobile Intel Pentium Processor III/440MX
	 Chipset Platform Design Guide
	 --------------------------------------------------------
	 Most insightful information on the Intel
         SpeedStep Technology Control Logic. Now if we knew what 
	 GPO(LO/HI) is connected to and how to control it...
	 Don't forget to program CPU_LCK and CPU_SEL (#5 on p.27),
         even though I have no idea (yet) on how to do that.

	 Unfortunately, GPO(LO/HI) doesn't seem to be connected to a
	 General Purpouse Output pin on 440BX chipsets. On Dave Jones'
	 and my own notebook GPO #0 changed between low and high
	 depending on the SpeedStep state, but setting it to the
	 different level had no effect on the CPU Frequency.

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I couldn't find any useful information on other vendor 
chipsets (VIA etc.) publicly available. Maybe I'll ask VIA sometimes,
but I really don't want to sign a NDA. 
