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#                     MOSIS distribution Version 4.1                  #
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# This is a version control header file for MOSIS's distribution of   #
# Magic related technology files and system libraries....             #
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#       Modified by Jen-I Pi, MOSIS Project, USC/ISI     10/01/1993    #
#       Please send bug reports/comments to mosis@mosis.edu :-)       #
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INTRODUCTION

  [*************************** Preliminary ***************************]
  MOSIS's distribution of Magic technolofy file for SCMOS technology
  now has CIFinput and CIFoutput section in templates so that it will
  be easier to maintain. It also supports two layers, "open" and
  "pstop" for micro-machined device fabrication in CMOS process as 
  described by Janet C. Marshall's paper in IEEE Circuit and Devices,
  Vol. 8, N0. 6, 1992. this layer is now in a 'preliminary' stage.
 
  This directory contains MOSIS's Magic technology file for Magic6.3
  HP's CMOS26B process (with three layer metal) is now included as
  the technology "lambda=0.5(gen). HP's 1.2um process with 'linear
  capacitor' (actually a well capacitor) is also include...
  Both Buried CCD devices and Bipolar NPN transistor are fully
  implemented for ORBIT's 2.0um low-noise process.

  Before installation, please read the file 'COPYRIGHT' for copyright
  notice.

INSTALLATION

  To install a technology file with this layer, simply type

     "make techfile" or "make install"

  to you system (Unix) prompt.

DOCUMENTATION

  In the doc subdirectory, you can find a preliminary PostScript file
  for MOSIS's SCMOS Technology Manual. Warning: This manualscript is
  in a very preliminary stage, if you have any problem with it don't
  hesitate to discuss it further with me...(pi@isi.edu)

EXAMPLE

  In the 'examples' subdirectory, we have:

  palette.mag - palette of all layers available in MOSIS's SCMOS tech-
	nology". Turn your DRC off before viewing it!!

  ccd.mag - An example of a buried channel CCD layout.

  float_gate.mag - An example of a floating-gate device.

  wellcap.mag - An example of layout of linear capacitors available
	from SCNLC technology, i.e. HP's 1.2um process.

  npn.mag - An example of a Bipolar NPN transistor layout. For ORBIT's
	2um lower-noise Analog process.

  large_npn.mag - A large NPN bipolar transistor consists of smalls
	unit transistors.

  all.mag - An example of part of the design rules... NOT Complete...

  m3padframe.mag - A TinyChip padframe for HP's 1.0um process. Notice
	that those m1 strip is required to complete a DRC free pad.
	These pads use all three metal layers.

  inf_source - An example of micromachined device fabrication. This
        layout is a reproduction of Fig. 8 of Janet C. Marshall's
	article titled "High Level Melds Micromachined Devices with
	Foundries", IEEE Circuits and Devices, Vol. 8, No. 6, pp.
	10-17, Nov. 1992.
	
BUGs

  send you bug report or suggestions to mosis@mosis.edu

Jen-I Pi **** 10/01/93
MOSIS Project, USC/ISI
(310) 8221511 x640






