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Date: Thu, 4 May 2006 17:34:48 GMT
From: Ted Mittelstaedt <tedm@ipinc.net>
Reply-To: Ted Mittelstaedt <tedm@ipinc.net>
To: FreeBSD-gnats-submit@freebsd.org
Cc:
Subject: Correction of kernel panic with Broadcom chip BCM5714C and other updates (fix included)
X-Send-Pr-Version: 3.113
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>Number:         96806
>Category:       kern
>Synopsis:       [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    jkim
>State:          closed
>Quarter:        
>Keywords:       
>Date-Required:  
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Fri May 05 00:40:19 GMT 2006
>Closed-Date:    Tue May 22 19:38:37 GMT 2007
>Last-Modified:  Tue May 22 19:38:37 GMT 2007
>Originator:     Ted Mittelstaedt
>Release:        FreeBSD 6.1-RC1 i386
>Organization:
Internet Partners, Inc.
>Environment:
System: FreeBSD ipinc-hp-test.ipinc.net 6.1-RC1 FreeBSD 6.1-RC1 #0: Thu May 4 16:13:49 UTC 2006 root@:/usr/src/sys/i386/compile/GENERIC i386


	
>Description:
	
Some versions of the HP DL320 G4 ship with a Broadcom ethernet chip
BCM5414C, this chip needs special exceptions in the bge driver or the
system will panic.  During the investigation to fix this while examining
the Broadcom-written Linux driver source available from their website,
I found that an old update to the bge driver, CVS revision 1.38 with the
notation:

"Change the short hand representation of the various ASIC revisions"

had bitwise manipulation shifts in it that I have been unable to find out
how exactly they produced the same magic numbers that were previously in
the FreeBSD code that they replaced.  I've tried many incantations BY HAND
to work these shifts and gotten nothing whatsoever that seems to agree.

Broadcom has expanded the list of magic numbers for various bugs in
subsequent chipsets they have released and these are all in the Broadcom
Linux driver, along with exceptions for the BCM5714, the BCM5780 and the
BCM5705 that are not in the FreeBSD driver.

I have removed the BGE_PCIDMARWCTL_RD_WAT_SHIFT and
BGE_PCIDMARWCTL_WR_WAT_SHIFT variables and put back in the list of magic
numbers from the Linux driver, this should also make it easier to maintain
in the future should Broadcom release yet more buggy chipsets.

I refuse to speculate further on how exactly the driver worked with this
error. :-)

I have also added a number of PCI chip ID's that were in the Broadcom
Linux driver that were not in the FreeBSD driver.  I have also corrected
the BCM5714 ASIC chip ID it was previously set at 0x05 but the Broadcom-
written driver has this set to 0x09, the result of the wrong chipset ID
was the one previous exception in the FreeBSD code for the BCM5714 dealing
with the ring buffer size wasn't even activated.

The result of these changes is that the Ethernet port #2 on the HP Proliant
DL320 G4 now works without panicing the system.  The Ethernet port #1 on the
DL320 G4 still does not work, this I mentioned in PR kern/94307.  I will
investigate that further at some future time and hopefully produce a patch
for it.  (fortunately most servers don't need 2 NICs)

>How-To-Repeat:
	
>Fix:

	

----------------------------------cut here patch to if_bge.c-------------------------------------
*** if_bge.c.dist	Sat Mar  4 09:34:48 2006
--- if_bge.c	Thu May  4 16:56:36 2006
***************
*** 152,167 ****
--- 152,179 ----
  		"Broadcom BCM5704C Dual Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
  		"Broadcom BCM5704S Dual Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_2,
+ 		"Broadcom BCM5704S v2 Dual Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
  		"Broadcom BCM5705 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
  		"Broadcom BCM5705K Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705F,
+ 		"Broadcom BCM5705F Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
  		"Broadcom BCM5705M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
  		"Broadcom BCM5705M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,
  		"Broadcom BCM5714C Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714S,
+ 		"Broadcom BCM5714S Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715,
+ 		"Broadcom BCM5715 Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715S,
+ 		"Broadcom BCM5715S Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5720,
+ 		"Broadcom BCM5720 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5721,
  		"Broadcom BCM5721 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
***************
*** 170,179 ****
--- 182,203 ----
  		"Broadcom BCM5750M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
  		"Broadcom BCM5751 Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751F,
+ 		"Broadcom BCM5751F Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,
  		"Broadcom BCM5751M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5752,
  		"Broadcom BCM5752 Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753F,
+ 		"Broadcom BCM5753F Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753M,
+ 		"Broadcom BCM5753M Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780,
+ 		"Broadcom BCM5780 Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780S,
+ 		"Broadcom BCM5780S Gigabit Ethernet" },
+ 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5781,
+ 		"Broadcom BCM5781 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
  		"Broadcom BCM5782 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
***************
*** 1048,1077 ****
  	/* Set up the PCI DMA control register. */
  	if (sc->bge_pcie) {
  		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
! 		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
  	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
  	    BGE_PCISTATE_PCI_BUSMODE) {
  		/* Conventional PCI bus */
! 		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 		    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
! 		    (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
! 		    (0x0F);
  	} else {
  		/* PCI-X bus */
  		/*
  		 * The 5704 uses a different encoding of read/write
  		 * watermarks.
  		 */
! 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
  			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 			    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
! 			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
! 		else
  			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 			    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
! 			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
! 			    (0x0F);
  
  		/*
  		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
--- 1072,1106 ----
  	/* Set up the PCI DMA control register. */
  	if (sc->bge_pcie) {
  		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 		    (0x180000);
  	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
  	    BGE_PCISTATE_PCI_BUSMODE) {
  		/* Conventional PCI bus */
! 			if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
! 					BGE_ASICREV_BCM5750) {
!                           dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
!                                 (0x3F0000); }
!          else 
! 			  dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 				(0x3F000F);
  	} else {
  		/* PCI-X bus */
  		/*
  		 * The 5704 uses a different encoding of read/write
  		 * watermarks.
  		 */
! 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704 || BGE_ASICREV_BCM5703)
! 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 			    (0x9F0000);
! 		else if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
! 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 			    (0x144000);
! 		else if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
  			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 			    (0x148000);
! 		else 
  			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
! 			    (0x1B000F);
  
  		/*
  		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
-----------------------------------cut here-------------------------------------------------


----------------------------------cut here patch to if_bgereg.h-----------------------------
*** if_bgereg.h.dist	Sun Feb  5 18:07:15 2006
--- if_bgereg.h	Thu May  4 17:18:06 2006
***************
*** 224,232 ****
  
  #define BGE_CHIPID_TIGON_I		0x40000000
  #define BGE_CHIPID_TIGON_II		0x60000000
  #define BGE_CHIPID_BCM5700_B0		0x71000000
! #define BGE_CHIPID_BCM5700_B1		0x71020000
! #define BGE_CHIPID_BCM5700_B2		0x71030000
  #define BGE_CHIPID_BCM5700_ALTIMA	0x71040000
  #define BGE_CHIPID_BCM5700_C0		0x72000000
  #define BGE_CHIPID_BCM5701_A0		0x00000000	/* grrrr */
--- 224,234 ----
  
  #define BGE_CHIPID_TIGON_I		0x40000000
  #define BGE_CHIPID_TIGON_II		0x60000000
+ #define BGE_CHIPID_BCM5700_A0		0x70000000
+ #define BGE_CHIPID_BCM5700_A1		0x70010000
  #define BGE_CHIPID_BCM5700_B0		0x71000000
! #define BGE_CHIPID_BCM5700_B1		0x71010000
! #define BGE_CHIPID_BCM5700_B3		0x71020000
  #define BGE_CHIPID_BCM5700_ALTIMA	0x71040000
  #define BGE_CHIPID_BCM5700_C0		0x72000000
  #define BGE_CHIPID_BCM5701_A0		0x00000000	/* grrrr */
***************
*** 236,251 ****
  #define BGE_CHIPID_BCM5703_A0		0x10000000
  #define BGE_CHIPID_BCM5703_A1		0x10010000
  #define BGE_CHIPID_BCM5703_A2		0x10020000
  #define BGE_CHIPID_BCM5704_A0		0x20000000
  #define BGE_CHIPID_BCM5704_A1		0x20010000
  #define BGE_CHIPID_BCM5704_A2		0x20020000
  #define BGE_CHIPID_BCM5705_A0		0x30000000
  #define BGE_CHIPID_BCM5705_A1		0x30010000
  #define BGE_CHIPID_BCM5705_A2		0x30020000
  #define BGE_CHIPID_BCM5705_A3		0x30030000
  #define BGE_CHIPID_BCM5750_A0		0x40000000
  #define BGE_CHIPID_BCM5750_A1		0x40010000
! #define BGE_CHIPID_BCM5714_A0		0x50000000
  
  /* shorthand one */
  #define BGE_ASICREV(x)			((x) >> 28)
--- 238,258 ----
  #define BGE_CHIPID_BCM5703_A0		0x10000000
  #define BGE_CHIPID_BCM5703_A1		0x10010000
  #define BGE_CHIPID_BCM5703_A2		0x10020000
+ #define BGE_CHIPID_BCM5703_A3		0x10030000
  #define BGE_CHIPID_BCM5704_A0		0x20000000
  #define BGE_CHIPID_BCM5704_A1		0x20010000
  #define BGE_CHIPID_BCM5704_A2		0x20020000
+ #define BGE_CHIPID_BCM5704_A3		0x20030000
  #define BGE_CHIPID_BCM5705_A0		0x30000000
  #define BGE_CHIPID_BCM5705_A1		0x30010000
  #define BGE_CHIPID_BCM5705_A2		0x30020000
  #define BGE_CHIPID_BCM5705_A3		0x30030000
  #define BGE_CHIPID_BCM5750_A0		0x40000000
  #define BGE_CHIPID_BCM5750_A1		0x40010000
! #define BGE_CHIPID_BCM5750_A3		0x40030000
! #define BGE_CHIPID_BCM5752_A0_HW	0x50000000
! #define BGE_CHIPID_BCM5752_A0		0x60000000
! #define BGE_CHIPID_BCM5752_A1		0x60010000
  
  /* shorthand one */
  #define BGE_ASICREV(x)			((x) >> 28)
***************
*** 255,262 ****
  #define BGE_ASICREV_BCM5704		0x02
  #define BGE_ASICREV_BCM5705		0x03
  #define BGE_ASICREV_BCM5750		0x04
- #define BGE_ASICREV_BCM5714		0x05
  #define BGE_ASICREV_BCM5752		0x06
  
  /* chip revisions */
  #define BGE_CHIPREV(x)			((x) >> 24)
--- 262,270 ----
  #define BGE_ASICREV_BCM5704		0x02
  #define BGE_ASICREV_BCM5705		0x03
  #define BGE_ASICREV_BCM5750		0x04
  #define BGE_ASICREV_BCM5752		0x06
+ #define BGE_ASICREV_BCM5780		0x08
+ #define BGE_ASICREV_BCM5714		0x09
  
  /* chip revisions */
  #define BGE_CHIPREV(x)			((x) >> 24)
***************
*** 264,269 ****
--- 272,282 ----
  #define BGE_CHIPREV_5700_BX		0x71
  #define BGE_CHIPREV_5700_CX		0x72
  #define BGE_CHIPREV_5701_AX		0x00
+ #define BGE_CHIPREV_5703_AX		0x10
+ #define BGE_CHIPREV_5704_AX		0x20
+ #define BGE_CHIPREV_5704_BX		0x21
+ #define BGE_CHIPREV_5750_AX		0x40
+ #define BGE_CHIPREV_5750_BX		0x41
  
  /* PCI DMA Read/Write Control register */
  #define BGE_PCIDMARWCTL_MINDMA		0x000000FF
***************
*** 271,279 ****
  #define BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
  #define BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x00004000
  #define BGE_PCIDMARWCTL_RD_WAT		0x00070000
- # define BGE_PCIDMARWCTL_RD_WAT_SHIFT	16
  #define BGE_PCIDMARWCTL_WR_WAT		0x00380000
- # define BGE_PCIDMARWCTL_WR_WAT_SHIFT	19
  #define BGE_PCIDMARWCTL_USE_MRM		0x00400000
  #define BGE_PCIDMARWCTL_ASRT_ALL_BE	0x00800000
  #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD	0x0F000000
--- 284,290 ----
***************
*** 1945,1961 ****
--- 1956,1984 ----
  #define BCOM_DEVICEID_BCM5703X		0x16C7
  #define BCOM_DEVICEID_BCM5704C		0x1648
  #define BCOM_DEVICEID_BCM5704S		0x16A8
+ #define BCOM_DEVICEID_BCM5704S_2	0x1649
  #define BCOM_DEVICEID_BCM5705		0x1653
+ #define BCOM_DEVICEID_BCM5705F		0x166E
  #define BCOM_DEVICEID_BCM5705K		0x1654
+ #define BCOM_DEVICEID_BCM5720		0x1658
  #define BCOM_DEVICEID_BCM5721		0x1659
  #define BCOM_DEVICEID_BCM5705M		0x165D
  #define BCOM_DEVICEID_BCM5705M_ALT	0x165E
  #define BCOM_DEVICEID_BCM5714C		0x1668
+ #define BCOM_DEVICEID_BCM5714S		0x1669
+ #define BCOM_DEVICEID_BCM5715		0x1678
+ #define BCOM_DEVICEID_BCM5715S		0x1679
  #define BCOM_DEVICEID_BCM5750		0x1676
  #define BCOM_DEVICEID_BCM5750M		0x167C
  #define BCOM_DEVICEID_BCM5751		0x1677
+ #define BCOM_DEVICEID_BCM5751F		0x167E
  #define BCOM_DEVICEID_BCM5751M		0x167D
  #define BCOM_DEVICEID_BCM5752		0x1600
+ #define BCOM_DEVICEID_BCM5753F		0x16FE
+ #define BCOM_DEVICEID_BCM5753M		0x16FD
+ #define BCOM_DEVICEID_BCM5780		0x166A
+ #define BCOM_DEVICEID_BCM5780S		0x166B
+ #define BCOM_DEVICEID_BCM5781		0x16DD
  #define BCOM_DEVICEID_BCM5782		0x1696
  #define BCOM_DEVICEID_BCM5788		0x169C
  #define BCOM_DEVICEID_BCM5789		0x169D
-----------------------------------------------------------cut here-----------------------------------------

Ted
>Release-Note:
>Audit-Trail:

From: Ted Mittelstaedt <tedm@ipinc-hp-test.ipinc.net>
To: bug-followup@freebsd.org, tedm@ipinc.net
Cc:  
Subject: Re: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Thu, 4 May 2006 21:47:23 GMT

 Geeze!  Some days you just never have any luck at all!
 
 The patch to if_bge.c has a stupid typo in it, here it is again, correct this
 time!
 
 *** if_bge.c.dist	Sat Mar  4 09:34:48 2006
 --- if_bge.c	Thu May  4 21:43:46 2006
 ***************
 *** 152,167 ****
 --- 152,179 ----
   		"Broadcom BCM5704C Dual Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
   		"Broadcom BCM5704S Dual Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_2,
 + 		"Broadcom BCM5704S v2 Dual Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
   		"Broadcom BCM5705 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
   		"Broadcom BCM5705K Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705F,
 + 		"Broadcom BCM5705F Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
   		"Broadcom BCM5705M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
   		"Broadcom BCM5705M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,
   		"Broadcom BCM5714C Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714S,
 + 		"Broadcom BCM5714S Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715,
 + 		"Broadcom BCM5715 Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715S,
 + 		"Broadcom BCM5715S Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5720,
 + 		"Broadcom BCM5720 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5721,
   		"Broadcom BCM5721 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
 ***************
 *** 170,179 ****
 --- 182,203 ----
   		"Broadcom BCM5750M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
   		"Broadcom BCM5751 Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751F,
 + 		"Broadcom BCM5751F Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,
   		"Broadcom BCM5751M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5752,
   		"Broadcom BCM5752 Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753F,
 + 		"Broadcom BCM5753F Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753M,
 + 		"Broadcom BCM5753M Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780,
 + 		"Broadcom BCM5780 Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780S,
 + 		"Broadcom BCM5780S Gigabit Ethernet" },
 + 	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5781,
 + 		"Broadcom BCM5781 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
   		"Broadcom BCM5782 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
 ***************
 *** 1048,1077 ****
   	/* Set up the PCI DMA control register. */
   	if (sc->bge_pcie) {
   		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 ! 		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
   	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
   	    BGE_PCISTATE_PCI_BUSMODE) {
   		/* Conventional PCI bus */
 ! 		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 		    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 ! 		    (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 ! 		    (0x0F);
   	} else {
   		/* PCI-X bus */
   		/*
   		 * The 5704 uses a different encoding of read/write
   		 * watermarks.
   		 */
 ! 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
   			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 			    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 ! 			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 ! 		else
   			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 			    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 ! 			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 ! 			    (0x0F);
   
   		/*
   		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 --- 1072,1106 ----
   	/* Set up the PCI DMA control register. */
   	if (sc->bge_pcie) {
   		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 		    (0x180000);
   	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
   	    BGE_PCISTATE_PCI_BUSMODE) {
   		/* Conventional PCI bus */
 ! 			if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
 ! 					BGE_ASICREV_BCM5750) {
 !                           dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 !                                 (0x3F0000); }
 !          else 
 ! 			  dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 				(0x3F000F);
   	} else {
   		/* PCI-X bus */
   		/*
   		 * The 5704 uses a different encoding of read/write
   		 * watermarks.
   		 */
 ! 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704 || BGE_ASICREV_BCM5703)
 ! 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 			    (0x9F0000);
 ! 		else if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
 ! 			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 			    (0x144000);
 ! 		else if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
   			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 			    (0x148000);
 ! 		else 
   			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 ! 			    (0x1B000F);
   
   		/*
   		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 

From: "Internet Partners, Inc. Tech Support" <support@ipinc.net>
To: <bug-followup@FreeBSD.org>, "Ted Mittelstaedt" <tedm@ipinc.net>
Cc:  
Subject: Re: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Tue, 16 May 2006 16:07:14 -0700

 Update on this patch,
 
   After testing, the system every once in a while displays:
 
 bge1: watchdog timeout -- resetting
 bge1: link state changed to DOWN
 bge1: link state changed to UP
 
 The problem happens when there's a lot of disk and network
 traffic at the same time.  cvsup seems to cause it quite a
 bit.
 
 Others have noticed the same thing, see PR's kern/94863 
 (5714 controller), kern/92090 (unknown controller), kern/68351
 (5704 controller)
 
 I have found with the machine I'm testing with that plugging
 the Broadcom interface into a 10BaseT hub will make the
 problem go away.  Of course, the chip sets itself up as
 10BaseT, half-duplex then.
 
 Gleb Smirnoff stated in PR kern/68351 that he needs
 hardware to work on this.

From: "Imri Zvik" <imriz@co.zahav.net.il>
To: <bug-followup@FreeBSD.org>
Cc: <tedm@ipinc.net>
Subject: Re: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Wed, 17 May 2006 20:37:36 +0300

 I'm suffering from the same issue in 6.1-STABLE.
 bge0@pci1:2:0:  class=3D0x020000 card=3D0x00cb0e11 chip=3D0x16a714e4 =
 rev=3D0x02
 hdr=3D0x00
     vendor   =3D 'Broadcom Corporation'
     device   =3D 'BCM5703X NetXtreme Gigabit Ethernet'
     class    =3D network
     subclass =3D ethernet
 bge1@pci4:2:0:  class=3D0x020000 card=3D0x00cb0e11 chip=3D0x16a714e4 =
 rev=3D0x02
 hdr=3D0x00
     vendor   =3D 'Broadcom Corporation'
     device   =3D 'BCM5703X NetXtreme Gigabit Ethernet'
     class    =3D network
     subclass =3D Ethernet
 
 I also see unexplained input errors:
 bge0   1500 <Link#1>      00:11:0a:30:95:e6 13924787  1954 16584611
 0     0
 
 May  8 14:51:46 leela kernel: bge0: watchdog timeout -- resetting
 May  8 14:51:46 leela kernel: bge0: link state changed to DOWN
 May  8 14:51:46 leela kernel: bge0: link state changed to UP
 May 12 12:39:24 leela kernel: bge1: watchdog timeout -- resetting
 May 12 12:39:24 leela kernel: bge1: link state changed to DOWN
 May 12 12:39:26 leela kernel: bge1: link state changed to UP
 May 13 20:01:21 leela kernel: bge1: watchdog timeout -- resetting
 May 13 20:01:21 leela kernel: bge1: link state changed to DOWN
 May 13 20:01:23 leela kernel: bge1: link state changed to UP

From: Yoshiaki Uchikawa <yoshiaki@kt.rim.or.jp>
To: bug-followup@FreeBSD.org, tedm@ipinc.net
Cc:  
Subject: Re: kern/96806 : [bge] [patch] Correction of kernel panic with
 Broadcom chip BCM5714C and other updates
Date: Wed, 24 May 2006 01:38:53 +0900 (JST)

 Hi,
 
 I used kern/96806 patch on IBM e326m.
 But, I have same problem as kern/94863 reported, occcurred.
 
   bge1: discard frame w/o leading ethernet header (len 4294967292 pkt len
  4294967292)
 
   And:
   Fatal trap 12: page fault while in kernel mode
   :
   :
 
 
  It seems there a part of initialization lack with kern/96806
  patch.
  I performed the one-line addition to if_bge.c .
  It seems to operate very well.
 
 --- if_bge.c.orig	Sat Mar  4 18:34:48 2006
 +++ if_bge.c	Fri Jan 14 16:25:09 2005
 @@ -152,16 +152,28 @@
  		"Broadcom BCM5704C Dual Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
  		"Broadcom BCM5704S Dual Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_2,
 +		"Broadcom BCM5704S v2 Dual Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
  		"Broadcom BCM5705 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
  		"Broadcom BCM5705K Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705F,
 +		"Broadcom BCM5705F Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
  		"Broadcom BCM5705M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
  		"Broadcom BCM5705M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,
  		"Broadcom BCM5714C Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714S,
 +		"Broadcom BCM5714S Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715,
 +		"Broadcom BCM5715 Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715S,
 +		"Broadcom BCM5715S Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5720,
 +		"Broadcom BCM5720 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5721,
  		"Broadcom BCM5721 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
 @@ -170,10 +182,22 @@
  		"Broadcom BCM5750M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
  		"Broadcom BCM5751 Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751F,
 +		"Broadcom BCM5751F Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,
  		"Broadcom BCM5751M Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5752,
  		"Broadcom BCM5752 Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753F,
 +		"Broadcom BCM5753F Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753M,
 +		"Broadcom BCM5753M Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780,
 +		"Broadcom BCM5780 Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780S,
 +		"Broadcom BCM5780S Gigabit Ethernet" },
 +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5781,
 +		"Broadcom BCM5781 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
  		"Broadcom BCM5782 Gigabit Ethernet" },
  	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
 @@ -1048,30 +1072,35 @@
  	/* Set up the PCI DMA control register. */
  	if (sc->bge_pcie) {
  		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 +		    (0x180000);
  	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
  	    BGE_PCISTATE_PCI_BUSMODE) {
  		/* Conventional PCI bus */
 -		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -		    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -		    (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 -		    (0x0F);
 +			if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
 +					BGE_ASICREV_BCM5750) {
 +                          dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 +                                (0x3F0000); }
 +         else 
 +			  dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 +				(0x3F000F);
  	} else {
  		/* PCI-X bus */
  		/*
  		 * The 5704 uses a different encoding of read/write
  		 * watermarks.
  		 */
 -		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 +		if (sc->bge_asicrev == BGE_ASICREV_BCM5704 || BGE_ASICREV_BCM5703)
  			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -			    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 -		else
 +			    (0x9F0000);
 +		else if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
 +			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 +			    (0x144000);
 +		else if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
 +			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 +			    (0x148000);
 +		else 
  			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -			    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 -			    (0x0F);
 +			    (0x1B000F);
  
  		/*
  		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 @@ -2103,7 +2132,8 @@
  	 * on this chip.
  	 */
  	if (sc->bge_asicrev == BGE_ASICREV_BCM5714 || 
 -            sc->bge_asicrev == BGE_ASICREV_BCM5752)
 +            sc->bge_asicrev == BGE_ASICREV_BCM5752 || 
 +            sc->bge_asicrev == BGE_ASICREV_BCM5780)
  		sc->bge_asicrev = BGE_ASICREV_BCM5750;
  
  	/*
 
 --
   yoshiaki@kt.rim.or.jp
   Yoshiaki UCHIKAWA

From: "Internet Partners, Inc. Tech Support" <support@ipinc.net>
To: "Yoshiaki Uchikawa" <yoshiaki@kt.rim.or.jp>, <bug-followup@FreeBSD.org>
Cc:  
Subject: RE: kern/96806 : [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Tue, 23 May 2006 11:42:18 -0700

 I agree, this should be in there, the Broadcom linux driver treats the
 BCM5780
 similarly to the BCM5714.  Probably should also update the comment line just
 above it to:
 
          * Treat the 5714, 5752, and the 5780 like the 5750 until we have
 more info
          * on this chip.
 
 Ted
 

From: "Internet Partners, Inc. Tech Support" <support@ipinc.net>
To: freebsd-bugs@FreeBSD.org
Cc:  
Subject: RE: kern/96806 : [bge] [patch] Correction of kernel panic with
	Broadcom chip BCM5714C and other updates
Date: Tue, 23 May 2006 18:50:08 GMT

 The following reply was made to PR kern/96806; it has been noted by GNATS.
 
 From: "Internet Partners, Inc. Tech Support" <support@ipinc.net>
 To: "Yoshiaki Uchikawa" <yoshiaki@kt.rim.or.jp>, <bug-followup@FreeBSD.org>
 Cc:  
 Subject: RE: kern/96806 : [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
 Date: Tue, 23 May 2006 11:42:18 -0700
 
  I agree, this should be in there, the Broadcom linux driver treats the
  BCM5780
  similarly to the BCM5714.  Probably should also update the comment line just
  above it to:
  
           * Treat the 5714, 5752, and the 5780 like the 5750 until we have
  more info
           * on this chip.
  
  Ted
  
 _______________________________________________
 freebsd-bugs@freebsd.org mailing list
 http://lists.freebsd.org/mailman/listinfo/freebsd-bugs
 To unsubscribe, send any mail to "freebsd-bugs-unsubscribe@freebsd.org"

From: Yoshiaki Uchikawa <yoshiaki@kt.rim.or.jp>
To: freebsd-bugs@FreeBSD.org
Cc:  
Subject: Re: kern/96806 : [bge] [patch] Correction of kernel panic with
 Broadcom chip BCM5714C and other updates
Date: Tue, 23 May 2006 16:40:24 GMT

 The following reply was made to PR kern/96806; it has been noted by GNATS.
 
 From: Yoshiaki Uchikawa <yoshiaki@kt.rim.or.jp>
 To: bug-followup@FreeBSD.org, tedm@ipinc.net
 Cc:  
 Subject: Re: kern/96806 : [bge] [patch] Correction of kernel panic with
  Broadcom chip BCM5714C and other updates
 Date: Wed, 24 May 2006 01:38:53 +0900 (JST)
 
  Hi,
  
  I used kern/96806 patch on IBM e326m.
  But, I have same problem as kern/94863 reported, occcurred.
  
    bge1: discard frame w/o leading ethernet header (len 4294967292 pkt len
   4294967292)
  
    And:
    Fatal trap 12: page fault while in kernel mode
    :
    :
  
  
   It seems there a part of initialization lack with kern/96806
   patch.
   I performed the one-line addition to if_bge.c .
   It seems to operate very well.
  
  --- if_bge.c.orig	Sat Mar  4 18:34:48 2006
  +++ if_bge.c	Fri Jan 14 16:25:09 2005
  @@ -152,16 +152,28 @@
   		"Broadcom BCM5704C Dual Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,
   		"Broadcom BCM5704S Dual Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_2,
  +		"Broadcom BCM5704S v2 Dual Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
   		"Broadcom BCM5705 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
   		"Broadcom BCM5705K Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705F,
  +		"Broadcom BCM5705F Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
   		"Broadcom BCM5705M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
   		"Broadcom BCM5705M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,
   		"Broadcom BCM5714C Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5714S,
  +		"Broadcom BCM5714S Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715,
  +		"Broadcom BCM5715 Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5715S,
  +		"Broadcom BCM5715S Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5720,
  +		"Broadcom BCM5720 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5721,
   		"Broadcom BCM5721 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
  @@ -170,10 +182,22 @@
   		"Broadcom BCM5750M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
   		"Broadcom BCM5751 Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751F,
  +		"Broadcom BCM5751F Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,
   		"Broadcom BCM5751M Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5752,
   		"Broadcom BCM5752 Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753F,
  +		"Broadcom BCM5753F Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5753M,
  +		"Broadcom BCM5753M Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780,
  +		"Broadcom BCM5780 Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5780S,
  +		"Broadcom BCM5780S Gigabit Ethernet" },
  +	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5781,
  +		"Broadcom BCM5781 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
   		"Broadcom BCM5782 Gigabit Ethernet" },
   	{ BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
  @@ -1048,30 +1072,35 @@
   	/* Set up the PCI DMA control register. */
   	if (sc->bge_pcie) {
   		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  -		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
  -		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
  +		    (0x180000);
   	} else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
   	    BGE_PCISTATE_PCI_BUSMODE) {
   		/* Conventional PCI bus */
  -		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  -		    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
  -		    (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
  -		    (0x0F);
  +			if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
  +					BGE_ASICREV_BCM5750) {
  +                          dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  +                                (0x3F0000); }
  +         else 
  +			  dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  +				(0x3F000F);
   	} else {
   		/* PCI-X bus */
   		/*
   		 * The 5704 uses a different encoding of read/write
   		 * watermarks.
   		 */
  -		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
  +		if (sc->bge_asicrev == BGE_ASICREV_BCM5704 || BGE_ASICREV_BCM5703)
   			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  -			    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
  -			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
  -		else
  +			    (0x9F0000);
  +		else if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
  +			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  +			    (0x144000);
  +		else if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
  +			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  +			    (0x148000);
  +		else 
   			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
  -			    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
  -			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
  -			    (0x0F);
  +			    (0x1B000F);
   
   		/*
   		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
  @@ -2103,7 +2132,8 @@
   	 * on this chip.
   	 */
   	if (sc->bge_asicrev == BGE_ASICREV_BCM5714 || 
  -            sc->bge_asicrev == BGE_ASICREV_BCM5752)
  +            sc->bge_asicrev == BGE_ASICREV_BCM5752 || 
  +            sc->bge_asicrev == BGE_ASICREV_BCM5780)
   		sc->bge_asicrev = BGE_ASICREV_BCM5750;
   
   	/*
  
  --
    yoshiaki@kt.rim.or.jp
    Yoshiaki UCHIKAWA
 _______________________________________________
 freebsd-bugs@freebsd.org mailing list
 http://lists.freebsd.org/mailman/listinfo/freebsd-bugs
 To unsubscribe, send any mail to "freebsd-bugs-unsubscribe@freebsd.org"
State-Changed-From-To: open->feedback 
State-Changed-By: glebius 
State-Changed-When: Fri Aug 11 13:10:25 UTC 2006 
State-Changed-Why:  
Since the time the PR was filed, we have had quite a lot 
of merges from NetBSD, that in their turn were taken 
from Linux driver. 

Particularly we had few 5714C specific fixes. 

Can you please upgrade your system to 6.1-STABLE 
and report what is the status of the problem now? 


Responsible-Changed-From-To: freebsd-bugs->glebius 
Responsible-Changed-By: glebius 
Responsible-Changed-When: Fri Aug 11 13:10:25 UTC 2006 
Responsible-Changed-Why:  
I'll handle this. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=96806 

From: "Ted Mittelstaedt" <tedm@toybox.placo.com>
To: <bug-followup@FreeBSD.org>
Cc:  
Subject: Re: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Fri, 15 Sep 2006 01:28:37 -0700

 This is a multi-part message in MIME format.
 
 ------=_NextPart_000_0003_01C6D866.44D632B0
 Content-Type: text/plain;
 	charset="iso-8859-1"
 Content-Transfer-Encoding: quoted-printable
 
 The bge driver in the 6.1-CURRENT seems to have fixed this
 problem, we have been using it for a month now on a busy
 server.  It also seems to have fixed the timeout problems.
 
 I've examined the updated Broadcom driver in FreeBSD=20
 CURRENT and it incorporates most of the fixes in the patch
 posted to this PR.
 
 However, there is still a difference between the Broadcom
 written Linux driver and the FreeBSD driver in the watermark shifts:
 
 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 
 etc.
 
 The logic in the FreeBSD driver is still wrong, insofar that if you=20
 do these shifts by hand, the values you get do not equal the
 values that the Linux driver is plugging into the chip.
 
 It's difficult to know which is the right way to do this - either using
 the FreeBSD logic, or the Broadcom-written "magic number"
 logic, as non of this is documented by Broadcom (at least,
 not in any datasheets that aren't available under NDA only)
 and it's also difficult to know if it really even matters what is
 plugged in at all, or whether the ethernet chip is even paying
 any attention at all to these registers.
 
 I still think it would be better to copy what Broadcom is doing
 in their Linux code, using the magic numbers, purely for ease of
 maintainability.  Maybe I'll produce a patch the next time that
 we buy another of these servers and go to deploy it.  But, I can't
 do any more testing on the server we have, as it's in production
 now.
 
 Ted
 
 
 ------=_NextPart_000_0003_01C6D866.44D632B0
 Content-Type: text/html;
 	charset="iso-8859-1"
 Content-Transfer-Encoding: quoted-printable
 
 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
 <HTML><HEAD>
 <META http-equiv=3DContent-Type content=3D"text/html; =
 charset=3Diso-8859-1">
 <META content=3D"MSHTML 6.00.2800.1555" name=3DGENERATOR>
 <STYLE></STYLE>
 </HEAD>
 <BODY bgColor=3D#ffffff>
 <DIV><FONT face=3DArial size=3D2>The bge driver in the 6.1-CURRENT seems =
 to have=20
 fixed this</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>problem, we have been using it for a =
 month now on a=20
 busy</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>server.&nbsp; It also seems to have =
 fixed the=20
 timeout problems.</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>I've examined the updated Broadcom =
 driver in=20
 FreeBSD </FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>CURRENT and </FONT><FONT face=3DArial =
 size=3D2>it=20
 incorporates most of the fixes in the patch</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>posted to this </FONT><FONT =
 face=3DArial=20
 size=3D2>PR.</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>However, there is still a difference =
 between the=20
 Broadcom</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>written Linux driver and the FreeBSD =
 driver in the=20
 watermark shifts:</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV>(0xf &lt;&lt; BGE_PCIDMARWCTL_RD_WAT_SHIFT) |<BR>(0x2 &lt;&lt;=20
 BGE_PCIDMARWCTL_WR_WAT_SHIFT);</DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>etc.</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>The logic in the FreeBSD driver is =
 still wrong,=20
 insofar that if you </FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>do these shifts by hand, the values you =
 get do not=20
 equal the</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>values that the Linux driver is =
 plugging into the=20
 chip.</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>It's difficult to know which is the =
 right way to do=20
 this - either using</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>the FreeBSD logic, or the =
 Broadcom-written "magic=20
 number"</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>logic, as non of this is documented by =
 Broadcom (at=20
 least,</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>not in any datasheets that aren't =
 available under=20
 NDA only)</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>and it's also difficult to know if it =
 really even=20
 matters what is</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>plugged in at all, or whether the =
 ethernet chip is=20
 even paying</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>any attention at all to these=20
 registers.</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>I still think it would be better to =
 copy what=20
 Broadcom is doing</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>in their Linux code, using the magic =
 numbers,=20
 purely for ease of</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>maintainability.&nbsp; Maybe I'll =
 produce a patch=20
 the next time that</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>we buy another of these servers and go =
 to deploy=20
 it.&nbsp; But, I can't</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>do any more testing on the server we =
 have, as it's=20
 in production</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2>now.</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2>Ted</FONT></DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
 <DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV></BODY></HTML>
 
 ------=_NextPart_000_0003_01C6D866.44D632B0--
 

From: Gleb Smirnoff <glebius@FreeBSD.org>
To: Ted Mittelstaedt <tedm@toybox.placo.com>
Cc: freebsd-gnats-submit@FreeBSD.org
Subject: Re: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Fri, 15 Sep 2006 12:36:02 +0400

 --/3yNEOqWowh/8j+e
 Content-Type: text/plain; charset=koi8-r
 Content-Disposition: inline
 
 On Fri, Sep 15, 2006 at 08:30:19AM +0000, Ted Mittelstaedt wrote:
 T>  The bge driver in the 6.1-CURRENT seems to have fixed this
 T>  problem, we have been using it for a month now on a busy
 T>  server.  It also seems to have fixed the timeout problems.
 T>  
 T>  I've examined the updated Broadcom driver in FreeBSD=20
 T>  CURRENT and it incorporates most of the fixes in the patch
 T>  posted to this PR.
 T>  
 T>  However, there is still a difference between the Broadcom
 T>  written Linux driver and the FreeBSD driver in the watermark shifts:
 T>  
 T>  (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 T>  (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 T>  
 T>  etc.
 T>  
 T>  The logic in the FreeBSD driver is still wrong, insofar that if you=20
 T>  do these shifts by hand, the values you get do not equal the
 T>  values that the Linux driver is plugging into the chip.
 T>
 T>  It's difficult to know which is the right way to do this - either using
 T>  the FreeBSD logic, or the Broadcom-written "magic number"
 T>  logic, as non of this is documented by Broadcom (at least,
 T>  not in any datasheets that aren't available under NDA only)
 T>  and it's also difficult to know if it really even matters what is
 T>  plugged in at all, or whether the ethernet chip is even paying
 T>  any attention at all to these registers.
 T>  
 T>  I still think it would be better to copy what Broadcom is doing
 T>  in their Linux code, using the magic numbers, purely for ease of
 T>  maintainability.  Maybe I'll produce a patch the next time that
 T>  we buy another of these servers and go to deploy it.  But, I can't
 T>  do any more testing on the server we have, as it's in production
 T>  now.
 
 The Linux driver isn't a specification or the one true implementation.
 
 This register is very tricky and its meaning differs very much between
 different chip revisions. I have asked David Christiansen for details,
 and with his help have prepared the attached patch. However, I am not
 urging to commit it because a) I don't have ability to test it on vast
 variety of cards b) the current code doesn't have any real issues, apart
 that it is not like Linux's.
 
 -- 
 Totus tuus, Glebius.
 GLEBIUS-RIPN GLEB-RIPE
 
 --/3yNEOqWowh/8j+e
 Content-Type: text/plain; charset=koi8-r
 Content-Disposition: attachment; filename="bge.dmarwctl"
 
 Index: if_bge.c
 ===================================================================
 RCS file: /home/ncvs/src/sys/dev/bge/if_bge.c,v
 retrieving revision 1.139
 diff -u -p -r1.139 if_bge.c
 --- if_bge.c	23 Aug 2006 11:32:54 -0000	1.139
 +++ if_bge.c	23 Aug 2006 15:18:22 -0000
 @@ -1005,36 +1005,48 @@ bge_chipinit(struct bge_softc *sc)
  		BGE_MEMWIN_WRITE(sc, i, 0);
  
  	/* Set up the PCI DMA control register. */
 +	dma_rw_ctl = BGE_PCIDMARWCTL_READ_CMD | BGE_PCIDMARWCTL_WRITE_CMD;
 +
 +	/* Bits 23, 22. */
 +	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 +	    sc->bge_asicrev == BGE_ASICREV_BCM5701 ||
 +	    sc->bge_asicrev == BGE_ASICREV_BCM5714)
 +		dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE |
 +		    BGE_PCIDMARWCTL_USE_MRM;
 +
 +	/* DMA watermarks: bits 21 - 19, 18 - 16. */
  	if (sc->bge_flags & BGE_FLAG_PCIE) {
 -		/* PCI Express bus */
 -		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -		    (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -		    (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 +		/*
 +		 * DMA read watermark not used on PCI-E.
 +		 * DMA write watermark set to 128 bytes.
 +		 */
 +		dma_rw_ctl |= (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
  	} else if (sc->bge_flags & BGE_FLAG_PCIX) {
 -		/* PCI-X bus */
 -		if (BGE_IS_5714_FAMILY(sc)) {
 -			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
 -			dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
 -			/* XXX magic values, Broadcom-supplied Linux driver */
 -			if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
 -				dma_rw_ctl |= (1 << 20) | (1 << 18) | 
 -				    BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 -			else
 -				dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
 -
 -		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 +		switch (sc->bge_asicrev) {
 +		case BGE_ASICREV_BCM5780:
 +			/* XXX: Linux driver magic values. */
 +			dma_rw_ctl |= (1 << 20) | (1 << 18) | 
 +			    BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 +			break;
 +		case BGE_ASICREV_BCM5714:
 +		case BGE_ASICREV_BCM5714_A0:
 +			/* XXX: Linux driver magic values. */
 +			dma_rw_ctl |= (1 << 20) | (1 << 18) |
 +			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
 +			break;
 +		case BGE_ASICREV_BCM5704:
  			/*
  			 * The 5704 uses a different encoding of read/write
 -			 * watermarks.
 +			 * watermarks: 384 bytes for write and 1536 for read.
  			 */
 -			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -			    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 -		else
 -			dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -			    (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -			    (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 -			    (0x0F);
 +			dma_rw_ctl |= (7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 +			    (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 +			break;
 +		default:
 +			/* All other chips: 384 for write and read. */
 +			dma_rw_ctl |= (3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 +			    (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 +		}
  
  		/*
  		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 @@ -1047,18 +1059,20 @@ bge_chipinit(struct bge_softc *sc)
  			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
  			if (tmp == 0x6 || tmp == 0x7)
  				dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 +
 +			/* Set bit 23 to enable PCIX hw bug fix. */
 +                        dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
  		}
  	} else
 -		/* Conventional PCI bus */
 -		dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 -		    (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 -		    (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 -		    (0x0F);
 -
 -	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 -	    sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
 -	    sc->bge_asicrev == BGE_ASICREV_BCM5705)
 -		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
 +		/* Conventional PCI bus: 1024 bytes for read and write. */
 +		dma_rw_ctl |= (7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 +		    (7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 +
 +	/* Set minimum DMA only for 5700 and 5701. */
 +	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 +	    sc->bge_asicrev == BGE_ASICREV_BCM5701)
 +		dma_rw_ctl |= 0xf;
 +
  	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
  
  	/*
 Index: if_bgereg.h
 ===================================================================
 RCS file: /home/ncvs/src/sys/dev/bge/if_bgereg.h,v
 retrieving revision 1.52
 diff -u -p -r1.52 if_bgereg.h
 --- if_bgereg.h	23 Aug 2006 11:32:54 -0000	1.52
 +++ if_bgereg.h	23 Aug 2006 15:16:12 -0000
 @@ -290,20 +290,25 @@
  #define BGE_CHIPREV_5701_AX		0x00
  
  /* PCI DMA Read/Write Control register */
 +#define BGE_PCIDMARWCTL_WRITE_CMD	0x70000000
 +#define BGE_PCIDMARWCTL_READ_CMD	0x06000000
 +
  #define BGE_PCIDMARWCTL_MINDMA		0x000000FF
  #define BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
  #define BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
  #define BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x00004000
 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL	0x00004000
 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL	0x00008000
  #define BGE_PCIDMARWCTL_RD_WAT		0x00070000
 -# define BGE_PCIDMARWCTL_RD_WAT_SHIFT	16
 +#define BGE_PCIDMARWCTL_RD_WAT_SHIFT	16
  #define BGE_PCIDMARWCTL_WR_WAT		0x00380000
 -# define BGE_PCIDMARWCTL_WR_WAT_SHIFT	19
 +#define BGE_PCIDMARWCTL_WR_WAT_SHIFT	19
  #define BGE_PCIDMARWCTL_USE_MRM		0x00400000
  #define BGE_PCIDMARWCTL_ASRT_ALL_BE	0x00800000
  #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD	0x0F000000
 -# define  BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT	24
 +#define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT	24
  #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD	0xF0000000
 -# define  BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT	28
 +#define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT	28
  
  #define BGE_PCI_READ_BNDRY_DISABLE	0x00000000
  #define BGE_PCI_READ_BNDRY_16BYTES	0x00000100
 @@ -2075,9 +2080,6 @@ struct bge_status_block {
  #define BGE_MEDIA_COPPER		0x00000010
  #define BGE_MEDIA_FIBER			0x00000020
  
 -#define BGE_PCI_READ_CMD		0x06000000
 -#define BGE_PCI_WRITE_CMD		0x70000000
 -
  #define BGE_TICKS_PER_SEC		1000000
  
  /*
 
 --/3yNEOqWowh/8j+e--
Responsible-Changed-From-To: glebius->jkim 
Responsible-Changed-By: glebius 
Responsible-Changed-When: Wed Mar 28 14:01:51 UTC 2007 
Responsible-Changed-Why:  
Let Jung-uk decide what to do with this PR. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=96806 

From: Jung-uk Kim <jkim@FreeBSD.org>
To: bug-followup@FreeBSD.org, tedm@ipinc.net
Cc: Gleb Smirnoff <glebius@FreeBSD.org>
Subject: Re: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Wed, 28 Mar 2007 19:46:05 -0400

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   charset="iso-8859-1"
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 As glibius said, the Linux driver is not perfect.  I am not sure 
 what's changed in Linux driver between yours and mine but this patch 
 is what I came up with today, i.e., -CURRENT vs. the latest Linux 
 driver (tg3 3.71b).  Please note that I have lowered DMA read 
 watermark setting for BCM5714 family in PCI-X mode from 4 to 2 
 because the bit is 'supposedly' reserved for the controller, i.e., 
 the largest setting is 2 (= 256 bytes).
 
 Jung-uk Kim
 
 --Boundary-00=_/4vCG0dYUYdSDtp
 Content-Type: text/x-diff;
   charset="iso-8859-1";
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 Content-Transfer-Encoding: 7bit
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 	filename="bge.diff"
 
 Index: if_bge.c
 ===================================================================
 RCS file: /home/ncvs/src/sys/dev/bge/if_bge.c,v
 retrieving revision 1.186
 diff -u -r1.186 if_bge.c
 --- if_bge.c	13 Mar 2007 00:41:55 -0000	1.186
 +++ if_bge.c	28 Mar 2007 23:04:33 -0000
 @@ -1122,60 +1122,60 @@
  	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
  		BGE_MEMWIN_WRITE(sc, i, 0);
  
 -	/* Set up the PCI DMA control register. */
 +	/*
 +	 * Set up the PCI DMA control register.
 +	 */
 +	dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
 +	    BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
  	if (sc->bge_flags & BGE_FLAG_PCIE) {
 -		/* PCI Express bus */
 -		dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
 -		    BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) |
 -		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2);
 +		/* Read watermark not used, 128 bytes for write. */
 +		dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
  	} else if (sc->bge_flags & BGE_FLAG_PCIX) {
 -		/* PCI-X bus */
  		if (BGE_IS_5714_FAMILY(sc)) {
 -			dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
 -			dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
 -			/* XXX magic values, Broadcom-supplied Linux driver */
 -			dma_rw_ctl |= (1 << 20) | (1 << 18);
 -			if (sc->bge_asicrev == BGE_ASICREV_BCM5780)
 -				dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 -			else
 -				dma_rw_ctl |= 1 << 15;
 -
 -		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 -			/*
 -			 * The 5704 uses a different encoding of read/write
 -			 * watermarks.
 -			 */
 -			dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
 -			    BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
 -			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3);
 -		else
 -			dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
 -			    BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) |
 -			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) |
 +			/* 256 bytes for read and write. */
 +			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
 +			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
 +			dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
 +			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
 +			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
 +		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 +			/* 1536 bytes for read, 384 bytes for write. */
 +			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
 +			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
 +		} else {
 +			/* 384 bytes for read and write. */
 +			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
 +			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
  			    0x0F;
 -
 -		/*
 -		 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 -		 * for hardware bugs.
 -		 */
 +		}
  		if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
  		    sc->bge_asicrev == BGE_ASICREV_BCM5704) {
  			uint32_t tmp;
  
 +			/* Set ONE_DMA_AT_ONCE for hardware workaround. */
  			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
 -			if (tmp == 0x6 || tmp == 0x7)
 -				dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 -		}
 -	} else
 -		/* Conventional PCI bus */
 -		dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
 -		    BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) |
 -		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) |
 -		    0x0F;
 +			if (tmp == 6 || tmp == 7)
 +				dma_rw_ctl |=
 +				    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
  
 +			/* Set PCI-X DMA write workaround. */
 +			dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
 +		}
 +	} else {
 +		/* Conventional PCI bus: 256 bytes for read and write. */
 +		dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
 +		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
 +
 +		if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
 +		    sc->bge_asicrev != BGE_ASICREV_BCM5750)
 +			dma_rw_ctl |= 0x0F;
 +	}
 +	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 +	    sc->bge_asicrev == BGE_ASICREV_BCM5701)
 +		dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
 +		    BGE_PCIDMARWCTL_ASRT_ALL_BE;
  	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 -	    sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
 -	    sc->bge_asicrev == BGE_ASICREV_BCM5705)
 +	    sc->bge_asicrev == BGE_ASICREV_BCM5704)
  		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
  	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
  
 Index: if_bgereg.h
 ===================================================================
 RCS file: /home/ncvs/src/sys/dev/bge/if_bgereg.h,v
 retrieving revision 1.71
 diff -u -r1.71 if_bgereg.h
 --- if_bgereg.h	9 Mar 2007 01:30:23 -0000	1.71
 +++ if_bgereg.h	28 Mar 2007 23:04:33 -0000
 @@ -316,7 +316,9 @@
  #define	BGE_PCIDMARWCTL_MINDMA		0x000000FF
  #define	BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
  #define	BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
 -#define	BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x00004000
 +#define	BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x0000C000
 +#define	BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL	0x00004000
 +#define	BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL	0x00008000
  #define	BGE_PCIDMARWCTL_RD_WAT		0x00070000
  #define	BGE_PCIDMARWCTL_WR_WAT		0x00380000
  #define	BGE_PCIDMARWCTL_USE_MRM		0x00400000
 
 --Boundary-00=_/4vCG0dYUYdSDtp--

From: "Ted Mittelstaedt" <tedm@ipinc.net>
To: "Jung-uk Kim" <jkim@FreeBSD.org>, <bug-followup@FreeBSD.org>
Cc: "Gleb Smirnoff" <glebius@FreeBSD.org>
Subject: RE: kern/96806: [bge] [patch] Correction of kernel panic with Broadcom chip BCM5714C and other updates
Date: Thu, 29 Mar 2007 10:38:14 -0700

 I didn't record which Linux driver I used, I had got it off the
 Broadcom website, though, not from a Linux distribution.
 
 The fixes that went into the BCM5714 driver in between FreeBSD 6.1-RELEASE
 and FreeBSD .2-RELEASE corrected all of the problems we were having
 with this chip on our HP DL320
 
 I have 2 of these DL320's in service with the 6.2-RELEASE driver, both
 are busy mailservers, and have had no problems.
 
 HOWEVER regardless of whether we make the other changes, I think
 the watermark change needs to be committeed,
 since the bit is reserved that could merely mean that in
 previous chip revisions it has not been used and so our touching it
 is being ignored.  But a future revision of chip Broadcom may use
 this and the driver could then have problems.
 
 I'll try to find another Broadcom system with a newer chip in it that
 I can test these driver revisions, and follow up on it.

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/96806: commit references a PR
Date: Tue, 22 May 2007 19:23:09 +0000 (UTC)

 jkim        2007-05-22 19:22:58 UTC
 
   FreeBSD src repository
 
   Modified files:
     sys/dev/bge          if_bge.c if_bgereg.h 
   Log:
   Rearrange DMA read/write control register settings based on document snippet
   provided by davidch via glebius.
   
   PR:             kern/96806
   
   Revision  Changes    Path
   1.193     +43 -43    src/sys/dev/bge/if_bge.c
   1.73      +3 -4      src/sys/dev/bge/if_bgereg.h
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State-Changed-From-To: feedback->closed 
State-Changed-By: jkim 
State-Changed-When: Tue May 22 19:36:16 UTC 2007 
State-Changed-Why:  
BCM5714C is already supported and the remaining patch is committed. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=96806 
>Unformatted:
