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Date: Wed, 23 Sep 2009 20:46:24 GMT
From: Sergei Cherveni <sergei.cherveni@gmail.com>
To: freebsd-gnats-submit@FreeBSD.org
Subject: msk  FIFO rx overrun
X-Send-Pr-Version: www-3.1
X-GNATS-Notify:

>Number:         139093
>Category:       kern
>Synopsis:       [msk] msk FIFO rx overrun
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    yongari
>State:          closed
>Quarter:        
>Keywords:       
>Date-Required:  
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Wed Sep 23 20:50:01 UTC 2009
>Closed-Date:    Fri Jun 24 00:51:19 UTC 2011
>Last-Modified:  Fri Jun 24 00:51:19 UTC 2011
>Originator:     Sergei Cherveni
>Release:        8.0-RC1
>Organization:
>Environment:
FreeBSD hp6830s 8.0-RC1 FreeBSD 8.0-RC1 #0: Mon Sep 21 22:17:00 EEST 2009     root@hp6830s:/usr/obj/usr/src/sys/GENERIC  i386

>Description:
Periodically (sometimes every 3-5 minutes) all network connections are stuck and in the same time in /var/log/messages appears a following (the same on the console):
kernel: msk0: Rx FIFO overrun

During these periods of time there is no ping replies, and iftop stops showing info about traffic. It shows blank screen instead of rows of connections.

Simple commands "ifconfig msk0 down; ifconfig msk0 up" does restore normal operation of msk.

#pciconf -lv
mskc0@pci0:134:0:0:     class=0x020000 card=0x30e9103c chip=0x436c11ab rev=0x00 hdr=0x00
    vendor     = 'Marvell Semiconductor (Was: Galileo Technology Ltd)'
    device     = 'Marvell 8072 Ethernet Nic (88E8072)'
    class      = network
    subclass   = ethernet

#ifconfig msk0
msk0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> metric 0 mtu 1500
        options=19b<RXCSUM,TXCSUM,VLAN_MTU,VLAN_HWTAGGING,VLAN_HWCSUM,TSO4>
        ether 00:24:81:66:55:01
        inet 10.9.12.2 netmask 0xffffff00 broadcast 10.9.12.255
        media: Ethernet autoselect (100baseTX <full-duplex>)
        status: active

>How-To-Repeat:
Just start downloading something and make ping to control address, then wait for 5 minutes

>Fix:


>Release-Note:
>Audit-Trail:
Responsible-Changed-From-To: freebsd-bugs->freebsd-net 
Responsible-Changed-By: linimon 
Responsible-Changed-When: Wed Sep 23 22:05:52 UTC 2009 
Responsible-Changed-Why:  
Over to maintainer(s). 

http://www.freebsd.org/cgi/query-pr.cgi?pr=139093 

From: Gleb Kurtsou <gleb.kurtsou@gmail.com>
To: bug-followup@FreeBSD.org, sergei.cherveni@gmail.com
Cc:  
Subject: Re: kern/139093: [msk] msk FIFO rx overrun
Date: Thu, 24 Sep 2009 03:23:49 +0300

 I'm also getting these messages: msk0: Rx FIFO overrun.
 But it's rather hard to trigger for me, and happens usually 1-2 times a
 week.
 
 Another problem that can be probably related, is that adapter doesn't
 properly initialize itself after boot with cable plugged in. I have to
 take it out and then insert back to make adapter see the media, and
 change status to active accordingly. It 100% reproducible.
 
 ~ % pciconf -lv
 mskc0@pci0:2:0:0:       class=0x020000 card=0x902d104d chip=0x435311ab rev=0x15 hdr=0x00
     vendor     = 'Marvell Semiconductor (Was: Galileo Technology Ltd)'
     device     = 'Gigabit (88E8039 - http://www.marvell.com/drivers/driverDis)'
     class      = network
     subclass   = ethernet
 
Responsible-Changed-From-To: freebsd-net->yongari 
Responsible-Changed-By: yongari 
Responsible-Changed-When: Mon Sep 28 22:20:50 UTC 2009 
Responsible-Changed-Why:  
Grab. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=139093 
State-Changed-From-To: open->feedback 
State-Changed-By: yongari 
State-Changed-When: Mon Sep 28 22:27:15 UTC 2009 
State-Changed-Why:  
I guess jhb@ also reported similar issue. He said the problem 
happens only on 1000baseT link and he couldn't reproduce the issue 
on 100baseTX link. I fixed a bug in e1000phy(4) which could be 
related with this so would you give it try on latest 
msk(4)/e1000(4)? 
Sorry, I don't have Yukon extreme so I have to rely on your report. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=139093 

From: Sergei Cherveni <sergei.cherveni@gmail.com>
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/139093: [msk] msk FIFO rx overrun
Date: Mon, 5 Oct 2009 14:25:31 +0300

 Well, I have repeated the problem with 8.0-RC1 -- in total another
 conditions: first issue was at home, with notebook (which has a msk NIC)
 connected to home pc. And now on the workplace the notebook is connected
 to LAN switch. An hour of active downloading caused the message "FIFO
 rx overrun" to appear.
 
 Now I start cvsup for update sources to latest versions.
 

From: Pyun YongHyeon <pyunyh@gmail.com>
To: Sergei Cherveni <sergei.cherveni@gmail.com>
Cc: yongari@freebsd.org, bug-followup@FreeBSD.org
Subject: Re: kern/139093: [msk] msk FIFO rx overrun
Date: Mon, 5 Oct 2009 12:52:26 -0700

 On Mon, Oct 05, 2009 at 12:00:14PM +0000, Sergei Cherveni wrote:
 > The following reply was made to PR kern/139093; it has been noted by GNATS.
 > 
 > From: Sergei Cherveni <sergei.cherveni@gmail.com>
 > To: bug-followup@FreeBSD.org
 > Cc:  
 > Subject: Re: kern/139093: [msk] msk FIFO rx overrun
 > Date: Mon, 5 Oct 2009 14:25:31 +0300
 > 
 >  Well, I have repeated the problem with 8.0-RC1 -- in total another
 >  conditions: first issue was at home, with notebook (which has a msk NIC)
 >  connected to home pc. And now on the workplace the notebook is connected
 >  to LAN switch. An hour of active downloading caused the message "FIFO
 >  rx overrun" to appear.
 >  
 
 The PR submitters controller is Yukon Extreme but I don't know your
 controller model number. Assuming you have the same controller, as
 I wrote in follow-up, does the issue happen on 100baseTX link?
 
 >  Now I start cvsup for update sources to latest versions.
 >  
 
 Ok, that may also helps a lot. Make sure you have latest msk(4) and
 e1000phy(4).

From: Sergei Cherveni <sergei.cherveni@gmail.com>
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/139093: [msk] msk FIFO rx overrun
Date: Tue, 13 Oct 2009 17:12:42 +0000

 After a week I have to say - there is no more problem with msk driver.
 I was connecting notebook direct to home pc NIC and to LAN switch, and
 had no one message about "FIFO rx overrun".
 All these tests were made on the 100baseTX full-duplex link with
 auto-negotiation.
 
 # uname -a
 FreeBSD hp6830s 8.0-RC1 FreeBSD 8.0-RC1 #0: Mon Oct  5 16:00:33 UTC
 2009     root@:/usr/obj/usr/src/sys/GENERIC  i386
 
 # ifconfig msk0
 msk0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> metric 0 mtu 1500
         options=19b<RXCSUM,TXCSUM,VLAN_MTU,VLAN_HWTAGGING,VLAN_HWCSUM,TSO4>
         ether 00:24:81:66:55:01
         inet 192.168.137.113 netmask 0xffffff00 broadcast 192.168.137.255
         media: Ethernet autoselect (100baseTX <full-duplex,flag0,flag1>)
         status: active
 
 #pciconf -lv
 mskc0@pci0:134:0:0:     class=0x020000 card=0x30e9103c chip=0x436c11ab
 rev=0x00 hdr=0x00
     vendor     = 'Marvell Semiconductor (Was: Galileo Technology Ltd)'
     device     = 'Marvell 8072 Ethernet Nic (88E8072)'
     class      = network
     subclass   = ethernet
 
 #dmesg
 mskc0: <Marvell Yukon 88E8072 Gigabit Ethernet> port 0x2000-0x20ff mem
 0xd0100000-0xd0103fff irq 17 at device 0.0 on pci134
 msk0: <Marvell Technology Group Ltd. Yukon EX Id 0xb5 Rev 0x02> on mskc0
 msk0: Ethernet address: 00:24:81:66:55:01
 miibus0: <MII bus> on msk0
 e1000phy0: <Marvell 88E1149 Gigabit PHY> PHY 0 on miibus0
 e1000phy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
 1000baseT-FDX, auto

From: Pyun YongHyeon <pyunyh@gmail.com>
To: Sergei Cherveni <sergei.cherveni@gmail.com>
Cc: yongari@freebsd.org, bug-followup@FreeBSD.org
Subject: Re: kern/139093: [msk] msk FIFO rx overrun
Date: Tue, 13 Oct 2009 11:22:16 -0700

 On Tue, Oct 13, 2009 at 05:20:03PM +0000, Sergei Cherveni wrote:
 > The following reply was made to PR kern/139093; it has been noted by GNATS.
 > 
 > From: Sergei Cherveni <sergei.cherveni@gmail.com>
 > To: bug-followup@FreeBSD.org
 > Cc:  
 > Subject: Re: kern/139093: [msk] msk FIFO rx overrun
 > Date: Tue, 13 Oct 2009 17:12:42 +0000
 > 
 >  After a week I have to say - there is no more problem with msk driver.
 >  I was connecting notebook direct to home pc NIC and to LAN switch, and
 >  had no one message about "FIFO rx overrun".
 
 Ok, you used latest msk(4)/e1000phy(4) in HEAD, right?
 
 >  All these tests were made on the 100baseTX full-duplex link with
 >  auto-negotiation.
 >  
 
 By chance, can you test it on 1000baseT link instead of 100baseTX?
 
 >  # uname -a
 >  FreeBSD hp6830s 8.0-RC1 FreeBSD 8.0-RC1 #0: Mon Oct  5 16:00:33 UTC
 >  2009     root@:/usr/obj/usr/src/sys/GENERIC  i386
 >  
 >  # ifconfig msk0
 >  msk0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> metric 0 mtu 1500
 >          options=19b<RXCSUM,TXCSUM,VLAN_MTU,VLAN_HWTAGGING,VLAN_HWCSUM,TSO4>
 >          ether 00:24:81:66:55:01
 >          inet 192.168.137.113 netmask 0xffffff00 broadcast 192.168.137.255
 >          media: Ethernet autoselect (100baseTX <full-duplex,flag0,flag1>)
 >          status: active
 >  
 >  #pciconf -lv
 >  mskc0@pci0:134:0:0:     class=0x020000 card=0x30e9103c chip=0x436c11ab
 >  rev=0x00 hdr=0x00
 >      vendor     = 'Marvell Semiconductor (Was: Galileo Technology Ltd)'
 >      device     = 'Marvell 8072 Ethernet Nic (88E8072)'
 >      class      = network
 >      subclass   = ethernet
 >  
 >  #dmesg
 >  mskc0: <Marvell Yukon 88E8072 Gigabit Ethernet> port 0x2000-0x20ff mem
 >  0xd0100000-0xd0103fff irq 17 at device 0.0 on pci134
 >  msk0: <Marvell Technology Group Ltd. Yukon EX Id 0xb5 Rev 0x02> on mskc0
 >  msk0: Ethernet address: 00:24:81:66:55:01
 >  miibus0: <MII bus> on msk0
 >  e1000phy0: <Marvell 88E1149 Gigabit PHY> PHY 0 on miibus0
 >  e1000phy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
 >  1000baseT-FDX, auto
State-Changed-From-To: feedback->open 
State-Changed-By: yongari 
State-Changed-When: Tue Oct 13 18:31:53 UTC 2009 
State-Changed-Why:  
feedback received. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=139093 

From: Sergei Cherveni <sergei.cherveni@gmail.com>
To: bug-followup@FreeBSD.org, pyunyh@gmail.com
Cc:  
Subject: Re: kern/139093: [msk] msk FIFO rx overrun
Date: Mon, 19 Oct 2009 21:16:05 +0300

 From: Pyun YongHyeon <pyunyh@gmail.com>
 To: Sergei Cherveni <sergei.cherveni@gmail.com>
 Cc: yongari@freebsd.org, bug-followup@FreeBSD.org
 Subject: Re: kern/139093: [msk] msk FIFO rx overrun
 Date: Tue, 13 Oct 2009 11:22:16 -0700
 
 > On Tue, Oct 13, 2009 at 05:20:03PM +0000, Sergei Cherveni wrote:
  >> The following reply was made to PR kern/139093; it has been noted by GNATS.
  >>
  >> From: Sergei Cherveni <sergei.cherveni@gmail.com>
  >> To: bug-followup@FreeBSD.org
  >> Cc:
  >> Subject: Re: kern/139093: [msk] msk FIFO rx overrun
  >> Date: Tue, 13 Oct 2009 17:12:42 +0000
  >>
  >>  After a week I have to say - there is no more problem with msk driver.
  >>  I was connecting notebook direct to home pc NIC and to LAN switch, and
  >>  had no one message about "FIFO rx overrun".
 
 > Ok, you used latest msk(4)/e1000phy(4) in HEAD, right?
 
 It was releng_8 on 5 october.
 Sorry, but I didn't understand what it means when you wrote "would you
 give it try on latest msk(4)/e1000(4)".
 
  >>  All these tests were made on the 100baseTX full-duplex link with
  >>  auto-negotiation.
  >>
 
 > By chance, can you test it on 1000baseT link instead of 100baseTX?
 
 The 1000baseT link does not work well - it has 30% packet loss with
 standard ping packet size and more than 50% loss with 1000-byte
 packets (connected to hp procurve switch). Well, I had installed
 windows7 and got the exactly same result so there may be hardware
 problem.
 
 Back to latest drivers in HEAD
 I've done csup with "tag=.", and then made the following (having
 RELENG_8 sources in /usr/src):
 
 cp HEAD/src/sys/dev/msk/* /sys/dev/msk
 cp HEAD/src/sys/dev/e1000/e1000_phy.* /sys/dev/e1000
 cd /sys/dev/msk && make all install
 
 Here I got the message:
 "make: don't know how to make all. Stop"
 
 It seems I missed something in system?
 Is there a way to update drivers without installing CURRENT from scratch?
 And maybe it would better to continue in freebsd-net@ - anyway there
 is no more problem with "msk FIFO rx overrun" in 8.0-RC1 :)
State-Changed-From-To: open->feedback 
State-Changed-By: yongari 
State-Changed-When: Mon May 23 22:44:36 UTC 2011 
State-Changed-Why:  
Could you try latest msk(4) on your box? Recently I fixed a couple 
stability issues of msk(4). I think you can install 8.2-RELEASE and 
use msk(4) in HEAD. 

- Download if_msk.c/if_mskreg.h from HEAD. 
- Manually change all instances of pci_find_cap to pci_find_extcap()  
in if_msk.c would make it build on 8.2-RELEASE.  
- Install new kernel and shutdown the box 
- Make sure to cold-start(i.e. unplug your system's power cord and 
replug it after waiting 30 seconds) before rebooting  

Let me know whether that makes any difference. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=139093 

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/139093: commit references a PR
Date: Wed, 22 Jun 2011 01:43:14 +0000 (UTC)

 Author: yongari
 Date: Wed Jun 22 01:42:52 2011
 New Revision: 223396
 URL: http://svn.freebsd.org/changeset/base/223396
 
 Log:
   MFC r222219,222221,222223,222226-222227,222231,222516:
     Merge all relevant changes from HEAD to fix long standing
     instability issues of msk(4).  To get desired effect of this
     merge, cold restarting is required because incorrectly programmed
     registers are not reset to default value.
     PR:	kern/114631, kern/116853, kern/139093, kern/144206,
   	kern/147824, kern/151169, kern/154591, kern/155636,
   	kern/156493
   
   r222219:
     Do not blindly clear entire GPHY control register. It seems some
     bits of the register is used for other purposes such that clearing
     these bits resulted in unexpected results such as corrupted RX
     frames or missing LE status updates.  For old controllers like
     Yukon EC it had no effect but it caused all kind of troubles on
     Yukon Supreme.
     This change shall improve stability of controllers like Yukon
     Ultra, Ultra2, Extreme, Optima and Supreme.
   
   r222221:
     Rework store and forward configuration of TX MAC FIFO. Basically it
     enables store and forward mode except for jumbo frame on Yukon
     Ultra.
   
   r222223:
     Do not configure RAM registers for controllers that do not have
     them.  These registers are defined only for Yukon XL, Yukon EC and
     Yukon FE.
   
   r222226:
     Make sure to enable all clocks before accessing registers.
     Releasing PHY from power down/COMA is done after enabling all
     clocks. While I'm here remove unnecessary controller reset.
   
   r222227:
     Do not touch ASF related register for controllers that do not have
     these registers. Also disable Watchdog of ASF microcontroller.
   
   r222231:
     When MTU is changed, check whether driver should be reinitialized or
     not.  If reinitialized is required, clear driver running flag.
   
   r222516:
     Correctly check MAC running status before disabling TX/RX MACs.
 
 Modified:
   stable/8/sys/dev/msk/if_msk.c
   stable/8/sys/dev/msk/if_mskreg.h
 Directory Properties:
   stable/8/sys/   (props changed)
   stable/8/sys/amd64/include/xen/   (props changed)
   stable/8/sys/cddl/contrib/opensolaris/   (props changed)
   stable/8/sys/contrib/dev/acpica/   (props changed)
   stable/8/sys/contrib/pf/   (props changed)
 
 Modified: stable/8/sys/dev/msk/if_msk.c
 ==============================================================================
 --- stable/8/sys/dev/msk/if_msk.c	Wed Jun 22 00:49:24 2011	(r223395)
 +++ stable/8/sys/dev/msk/if_msk.c	Wed Jun 22 01:42:52 2011	(r223396)
 @@ -562,7 +562,7 @@ msk_miibus_statchg(device_t dev)
  		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
  		/* Disable Rx/Tx MAC. */
  		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
 -		if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
 +		if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
  			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
  			/* Read again to ensure writing. */
 @@ -1030,7 +1030,10 @@ msk_ioctl(struct ifnet *ifp, u_long comm
  				}
  			}
  			ifp->if_mtu = ifr->ifr_mtu;
 -			msk_init_locked(sc_if);
 +			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 +				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 +				msk_init_locked(sc_if);
 +			}
  		}
  		MSK_IF_UNLOCK(sc_if);
  		break;
 @@ -1212,37 +1215,30 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 -		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 +		our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 +		our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
  				/* Deassert Low Power for 1st PHY. */
 -				val |= PCI_Y2_PHY1_COMA;
 +				our |= PCI_Y2_PHY1_COMA;
  				if (sc->msk_num_port > 1)
 -					val |= PCI_Y2_PHY2_COMA;
 +					our |= PCI_Y2_PHY2_COMA;
  			}
  		}
 -		/* Release PHY from PowerDown/COMA mode. */
 -		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
 -		switch (sc->msk_hw_id) {
 -		case CHIP_ID_YUKON_EC_U:
 -		case CHIP_ID_YUKON_EX:
 -		case CHIP_ID_YUKON_FE_P:
 -		case CHIP_ID_YUKON_UL_2:
 -		case CHIP_ID_YUKON_OPT:
 -			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 -
 -			/* Enable all clocks. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 -			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
 -			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 +			val &= (PCI_FORCE_ASPM_REQUEST |
 +			    PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
 +			    PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 -			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 +			val &= PCI_CTL_TIM_VMAIN_AV_MSK;
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
  			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
 +			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1251,10 +1247,10 @@ msk_phy_power(struct msk_softc *sc, int 
  			val |= GLB_GPIO_STAT_RACE_DIS;
  			CSR_WRITE_4(sc, B2_GP_IO, val);
  			CSR_READ_4(sc, B2_GP_IO);
 -			break;
 -		default:
 -			break;
  		}
 +		/* Release PHY from PowerDown/COMA mode. */
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
 +
  		for (i = 0; i < sc->msk_num_port; i++) {
  			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
  			    GMLC_RST_SET);
 @@ -1300,28 +1296,33 @@ mskc_reset(struct msk_softc *sc)
  	bus_addr_t addr;
  	uint16_t status;
  	uint32_t val;
 -	int i;
 -
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	int i, initram;
  
  	/* Disable ASF. */
 -	if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
 -		status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 -		/* Clear AHB bridge & microcontroller reset. */
 -		status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 -		    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 -		/* Clear ASF microcontroller state. */
 -		status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 -		CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 -	} else
 -		CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 -	CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 -
 -	/*
 -	 * Since we disabled ASF, S/W reset is required for Power Management.
 -	 */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
 +	    sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +			status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 +			/* Clear AHB bridge & microcontroller reset. */
 +			status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 +			    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 +			/* Clear ASF microcontroller state. */
 +			status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 +			status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
 +			CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +		} else
 +			CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 +		CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 +		/*
 +		 * Since we disabled ASF, S/W reset is required for
 +		 * Power Management.
 +		 */
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	}
  
  	/* Clear all error bits in the PCI status register. */
  	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
 @@ -1362,8 +1363,8 @@ mskc_reset(struct msk_softc *sc)
  	/* Reset GPHY/GMAC Control */
  	for (i = 0; i < sc->msk_num_port; i++) {
  		/* GPHY Control reset. */
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
  		/* GMAC Control reset. */
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
 @@ -1396,8 +1397,14 @@ mskc_reset(struct msk_softc *sc)
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  
 +	initram = 0;
 +	if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_EC ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_FE)
 +		initram++;
 +
  	/* Configure timeout values. */
 -	for (i = 0; i < sc->msk_num_port; i++) {
 +	for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
 @@ -1708,6 +1715,9 @@ mskc_attach(device_t dev)
  		}
  	}
  
 +	/* Enable all clocks before accessing any registers. */
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +
  	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
  	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
 @@ -1748,9 +1758,6 @@ mskc_attach(device_t dev)
  	resource_int_value(device_get_name(dev), device_get_unit(dev),
  	    "int_holdoff", &sc->msk_int_holdoff);
  
 -	/* Soft reset. */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
  	/* Check number of MACs. */
  	sc->msk_num_port = 1;
 @@ -2964,6 +2971,7 @@ mskc_resume(device_t dev)
  
  	MSK_LOCK(sc);
  
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
  	mskc_reset(sc);
  	for (i = 0; i < sc->msk_num_port; i++) {
  		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
 @@ -3655,37 +3663,24 @@ msk_set_tx_stfwd(struct msk_if_softc *sc
  
  	ifp = sc_if->msk_ifp;
  	sc = sc_if->msk_softc;
 -	switch (sc->msk_hw_id) {
 -	case CHIP_ID_YUKON_EX:
 -		if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
 -			goto yukon_ex_workaround;
 -		if (ifp->if_mtu > ETHERMTU)
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_ENA);
 -		else
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 -		break;
 -	default:
 -yukon_ex_workaround:
 +	if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
 +	    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
 +	    sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
 +		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +		    TX_STFW_ENA);
 +	} else {
  		if (ifp->if_mtu > ETHERMTU) {
  			/* Set Tx GMAC FIFO Almost Empty Threshold. */
  			CSR_WRITE_4(sc,
  			    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
  			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
  			/* Disable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_DIS);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_DIS);
  		} else {
 -			/* Enable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_ENA);
  		}
 -		break;
  	}
  }
  
 
 Modified: stable/8/sys/dev/msk/if_mskreg.h
 ==============================================================================
 --- stable/8/sys/dev/msk/if_mskreg.h	Wed Jun 22 00:49:24 2011	(r223395)
 +++ stable/8/sys/dev/msk/if_mskreg.h	Wed Jun 22 01:42:52 2011	(r223396)
 @@ -677,6 +677,7 @@
  /* ASF Subsystem Registers (Yukon-2 only) */
  #define B28_Y2_SMB_CONFIG	0x0e40	/* 32 bit ASF SMBus Config Register */
  #define B28_Y2_SMB_CSD_REG	0x0e44	/* 32 bit ASF SMB Control/Status/Data */
 +#define B28_Y2_CPU_WDOG		0x0e48	/* 32 bit Watchdog Register */
  #define B28_Y2_ASF_IRQ_V_BASE	0x0e60	/* 32 bit ASF IRQ Vector Base */
  #define B28_Y2_ASF_STAT_CMD	0x0e68	/* 32 bit ASF Status and Command Reg */
  #define B28_Y2_ASF_HCU_CCSR	0x0e68	/* 32 bit ASF HCU CCSR (Yukon EX) */
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From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/139093: commit references a PR
Date: Wed, 22 Jun 2011 01:44:19 +0000 (UTC)

 Author: yongari
 Date: Wed Jun 22 01:44:09 2011
 New Revision: 223397
 URL: http://svn.freebsd.org/changeset/base/223397
 
 Log:
   MFC r222219,222221,222223,222226-222227,222231,222516:
     Merge all relevant changes from HEAD to fix long standing
     instability issues of msk(4).  To get desired effect of this
     merge, cold restarting is required because incorrectly programmed
     registers are not reset to default value.
     PR:	kern/114631, kern/116853, kern/139093, kern/144206,
   	kern/147824, kern/151169, kern/154591, kern/155636,
   	kern/156493
   
   r222219:
     Do not blindly clear entire GPHY control register. It seems some
     bits of the register is used for other purposes such that clearing
     these bits resulted in unexpected results such as corrupted RX
     frames or missing LE status updates.  For old controllers like
     Yukon EC it had no effect but it caused all kind of troubles on
     Yukon Supreme.
     This change shall improve stability of controllers like Yukon
     Ultra, Ultra2, Extreme, Optima and Supreme.
   
   r222221:
     Rework store and forward configuration of TX MAC FIFO. Basically it
     enables store and forward mode except for jumbo frame on Yukon
     Ultra.
   
   r222223:
     Do not configure RAM registers for controllers that do not have
     them.  These registers are defined only for Yukon XL, Yukon EC and
     Yukon FE.
   
   r222226:
     Make sure to enable all clocks before accessing registers.
     Releasing PHY from power down/COMA is done after enabling all
     clocks. While I'm here remove unnecessary controller reset.
   
   r222227:
     Do not touch ASF related register for controllers that do not have
     these registers. Also disable Watchdog of ASF microcontroller.
   
   r222231:
     When MTU is changed, check whether driver should be reinitialized or
     not.  If reinitialized is required, clear driver running flag.
   
   r222516:
     Correctly check MAC running status before disabling TX/RX MACs.
 
 Modified:
   stable/7/sys/dev/msk/if_msk.c
   stable/7/sys/dev/msk/if_mskreg.h
 Directory Properties:
   stable/7/sys/   (props changed)
   stable/7/sys/cddl/contrib/opensolaris/   (props changed)
   stable/7/sys/contrib/dev/acpica/   (props changed)
   stable/7/sys/contrib/pf/   (props changed)
 
 Modified: stable/7/sys/dev/msk/if_msk.c
 ==============================================================================
 --- stable/7/sys/dev/msk/if_msk.c	Wed Jun 22 01:42:52 2011	(r223396)
 +++ stable/7/sys/dev/msk/if_msk.c	Wed Jun 22 01:44:09 2011	(r223397)
 @@ -562,7 +562,7 @@ msk_miibus_statchg(device_t dev)
  		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
  		/* Disable Rx/Tx MAC. */
  		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
 -		if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
 +		if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
  			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
  			/* Read again to ensure writing. */
 @@ -1030,7 +1030,10 @@ msk_ioctl(struct ifnet *ifp, u_long comm
  				}
  			}
  			ifp->if_mtu = ifr->ifr_mtu;
 -			msk_init_locked(sc_if);
 +			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 +				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 +				msk_init_locked(sc_if);
 +			}
  		}
  		MSK_IF_UNLOCK(sc_if);
  		break;
 @@ -1212,37 +1215,30 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 -		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 +		our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 +		our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
  				/* Deassert Low Power for 1st PHY. */
 -				val |= PCI_Y2_PHY1_COMA;
 +				our |= PCI_Y2_PHY1_COMA;
  				if (sc->msk_num_port > 1)
 -					val |= PCI_Y2_PHY2_COMA;
 +					our |= PCI_Y2_PHY2_COMA;
  			}
  		}
 -		/* Release PHY from PowerDown/COMA mode. */
 -		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
 -		switch (sc->msk_hw_id) {
 -		case CHIP_ID_YUKON_EC_U:
 -		case CHIP_ID_YUKON_EX:
 -		case CHIP_ID_YUKON_FE_P:
 -		case CHIP_ID_YUKON_UL_2:
 -		case CHIP_ID_YUKON_OPT:
 -			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 -
 -			/* Enable all clocks. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 -			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
 -			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 +			val &= (PCI_FORCE_ASPM_REQUEST |
 +			    PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
 +			    PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 -			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 +			val &= PCI_CTL_TIM_VMAIN_AV_MSK;
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
  			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
 +			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1251,10 +1247,10 @@ msk_phy_power(struct msk_softc *sc, int 
  			val |= GLB_GPIO_STAT_RACE_DIS;
  			CSR_WRITE_4(sc, B2_GP_IO, val);
  			CSR_READ_4(sc, B2_GP_IO);
 -			break;
 -		default:
 -			break;
  		}
 +		/* Release PHY from PowerDown/COMA mode. */
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
 +
  		for (i = 0; i < sc->msk_num_port; i++) {
  			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
  			    GMLC_RST_SET);
 @@ -1300,28 +1296,33 @@ mskc_reset(struct msk_softc *sc)
  	bus_addr_t addr;
  	uint16_t status;
  	uint32_t val;
 -	int i;
 -
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	int i, initram;
  
  	/* Disable ASF. */
 -	if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
 -		status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 -		/* Clear AHB bridge & microcontroller reset. */
 -		status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 -		    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 -		/* Clear ASF microcontroller state. */
 -		status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 -		CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 -	} else
 -		CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 -	CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 -
 -	/*
 -	 * Since we disabled ASF, S/W reset is required for Power Management.
 -	 */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
 +	    sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +			status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 +			/* Clear AHB bridge & microcontroller reset. */
 +			status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 +			    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 +			/* Clear ASF microcontroller state. */
 +			status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 +			status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
 +			CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +		} else
 +			CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 +		CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 +		/*
 +		 * Since we disabled ASF, S/W reset is required for
 +		 * Power Management.
 +		 */
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	}
  
  	/* Clear all error bits in the PCI status register. */
  	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
 @@ -1362,8 +1363,8 @@ mskc_reset(struct msk_softc *sc)
  	/* Reset GPHY/GMAC Control */
  	for (i = 0; i < sc->msk_num_port; i++) {
  		/* GPHY Control reset. */
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
  		/* GMAC Control reset. */
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
 @@ -1396,8 +1397,14 @@ mskc_reset(struct msk_softc *sc)
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  
 +	initram = 0;
 +	if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_EC ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_FE)
 +		initram++;
 +
  	/* Configure timeout values. */
 -	for (i = 0; i < sc->msk_num_port; i++) {
 +	for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
 @@ -1708,6 +1715,9 @@ mskc_attach(device_t dev)
  		}
  	}
  
 +	/* Enable all clocks before accessing any registers. */
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +
  	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
  	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
 @@ -1748,9 +1758,6 @@ mskc_attach(device_t dev)
  	resource_int_value(device_get_name(dev), device_get_unit(dev),
  	    "int_holdoff", &sc->msk_int_holdoff);
  
 -	/* Soft reset. */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
  	/* Check number of MACs. */
  	sc->msk_num_port = 1;
 @@ -2964,6 +2971,7 @@ mskc_resume(device_t dev)
  
  	MSK_LOCK(sc);
  
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
  	mskc_reset(sc);
  	for (i = 0; i < sc->msk_num_port; i++) {
  		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
 @@ -3655,37 +3663,24 @@ msk_set_tx_stfwd(struct msk_if_softc *sc
  
  	ifp = sc_if->msk_ifp;
  	sc = sc_if->msk_softc;
 -	switch (sc->msk_hw_id) {
 -	case CHIP_ID_YUKON_EX:
 -		if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
 -			goto yukon_ex_workaround;
 -		if (ifp->if_mtu > ETHERMTU)
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_ENA);
 -		else
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 -		break;
 -	default:
 -yukon_ex_workaround:
 +	if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
 +	    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
 +	    sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
 +		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +		    TX_STFW_ENA);
 +	} else {
  		if (ifp->if_mtu > ETHERMTU) {
  			/* Set Tx GMAC FIFO Almost Empty Threshold. */
  			CSR_WRITE_4(sc,
  			    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
  			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
  			/* Disable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_DIS);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_DIS);
  		} else {
 -			/* Enable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_ENA);
  		}
 -		break;
  	}
  }
  
 
 Modified: stable/7/sys/dev/msk/if_mskreg.h
 ==============================================================================
 --- stable/7/sys/dev/msk/if_mskreg.h	Wed Jun 22 01:42:52 2011	(r223396)
 +++ stable/7/sys/dev/msk/if_mskreg.h	Wed Jun 22 01:44:09 2011	(r223397)
 @@ -677,6 +677,7 @@
  /* ASF Subsystem Registers (Yukon-2 only) */
  #define B28_Y2_SMB_CONFIG	0x0e40	/* 32 bit ASF SMBus Config Register */
  #define B28_Y2_SMB_CSD_REG	0x0e44	/* 32 bit ASF SMB Control/Status/Data */
 +#define B28_Y2_CPU_WDOG		0x0e48	/* 32 bit Watchdog Register */
  #define B28_Y2_ASF_IRQ_V_BASE	0x0e60	/* 32 bit ASF IRQ Vector Base */
  #define B28_Y2_ASF_STAT_CMD	0x0e68	/* 32 bit ASF Status and Command Reg */
  #define B28_Y2_ASF_HCU_CCSR	0x0e68	/* 32 bit ASF HCU CCSR (Yukon EX) */
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State-Changed-From-To: feedback->closed 
State-Changed-By: yongari 
State-Changed-When: Fri Jun 24 00:50:58 UTC 2011 
State-Changed-Why:  
Fix merged to both stable/8 and stable/7. If you encounter the 
issue again please open a new PR. 
Thanks for reporting! 

http://www.freebsd.org/cgi/query-pr.cgi?pr=139093 
>Unformatted:
