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Date: Mon, 16 Jul 2007 13:36:32 GMT
From: Alexander Shikoff <minotaur@crete.org.ua>
To: freebsd-gnats-submit@FreeBSD.org
Subject: "Tx descriptor error" with Marvell Yukon 
X-Send-Pr-Version: www-3.0

>Number:         114631
>Category:       kern
>Synopsis:       [msk] "Tx descriptor error" with Marvell Yukon
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    yongari
>State:          closed
>Quarter:        
>Keywords:       
>Date-Required:  
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Mon Jul 16 13:40:02 GMT 2007
>Closed-Date:    Fri Jun 24 00:48:43 UTC 2011
>Last-Modified:  Fri Jun 24 00:48:43 UTC 2011
>Originator:     Alexander Shikoff
>Release:        RELENG_6
>Organization:
>Environment:
FreeBSD typhoon 6.2-STABLE FreeBSD 6.2-STABLE #0: Mon Jul 16 15:09:38 EEST 2007     root@:/usr/obj/usr/src/sys/TYPHOON  i386

>Description:
I have a problem with Marvell Yukon network adapter:
mskc0: <Marvell Yukon 88E8056 Gigabit Ethernet> port 0x7000-0x70ff mem 0xf1000000-0xf1003fff irq 17 at device 0.0 on pci2
msk0: <Marvell Technology Group Ltd. Yukon EC Ultra Id 0xb4 Rev 0x03> on mskc0
msk0: Ethernet address: 00:1a:4d:43:55:b0
miibus0: <MII bus> on msk0
e1000phy0: <Marvell 88E1149 Gigabit PHY> on miibus0
e1000phy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseTX-FDX, auto
mskc0: [FAST]

Even with small traffic msk0 hangs and I see a couple of errors printed
on console:

mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
mskc0: Tx descriptor error
msk0: watchdog timeot

The second issue is when I'm bringing down msk0 interface with "ifconfig
msk0 down" the route to directly connected network does not dissapear
from routing table.
>How-To-Repeat:
1. Connect msk interface to 100BaseTX switch port. Try to make some
   traffic via msk (for example with csup).

2. When you got "mskc0: Tx descriptor error" try to bring msk down with
   ifconfig msk0 down and check routing table. 
>Fix:


>Release-Note:
>Audit-Trail:
Responsible-Changed-From-To: freebsd-bugs->yongari 
Responsible-Changed-By: yongari 
Responsible-Changed-When: Wed Jul 18 04:51:14 UTC 2007 
Responsible-Changed-Why:  
Grab. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=114631 
State-Changed-From-To: open->feedback 
State-Changed-By: yongari 
State-Changed-When: Wed Jul 18 05:03:36 UTC 2007 
State-Changed-Why:  
Would you show me verbosed boot message related with msk(4)? 

Btw, in order to remove route directly connected with network 
interface you may have to use "ifconfig msk0 inet delete". 

http://www.freebsd.org/cgi/query-pr.cgi?pr=114631 

From: Alexander Shikoff <minotaur@crete.org.ua>
To: yongari@FreeBSD.org
Cc:  
Subject: Re: kern/114631: [msk] "Tx descriptor error" with Marvell Yukon
Date: Wed, 18 Jul 2007 11:08:48 +0300

 On Wed, Jul 18, 2007 at 05:04:20AM +0000, yongari@FreeBSD.org wrote:
 > Synopsis: [msk] "Tx descriptor error" with Marvell Yukon
 > 
 > State-Changed-From-To: open->feedback
 > State-Changed-By: yongari
 > State-Changed-When: Wed Jul 18 05:03:36 UTC 2007
 > State-Changed-Why: 
 > Would you show me verbosed boot message related with msk(4)?
 > Btw, in order to remove route directly connected with network
 > interface you may have to use "ifconfig msk0 inet delete".
 >
 > http://www.freebsd.org/cgi/query-pr.cgi?pr=114631
 
 Before I put here a lot of output I would like to add a comment.
 Bringing interface down removes route properly. That was my failure while
 playing with same IP on different interfaces.
 
 
 In my case if_msk is compiled into kernel by adding "device msk" into kernel 
 config file. Additionally, my make.conf includes CPUTYPE?=pentium4.
 
 Here is output got with boot_verbose="YES" and verbose_loading="YES" in
 /boot/loader.conf. Here typhoon# is a host witn problematic msk-interface,
 rhost# - remote host.
 
 mskc0: <Marvell Yukon 88E8056 Gigabit Ethernet> port 0x7000-0x70ff mem 0xf1000000-0xf1003fff irq 17 at device 0.0
  on pci2
 mskc0: Reserved 0x4000 bytes for rid 0x10 type 3 at 0xf1000000
 mskc0: MSI count : 0
 mskc0: RAM buffer size : 128KB
 mskc0: Port 0 : Rx Queue 96KB(0x00000000:0x00017fff)
 mskc0: Port 0 : Tx Queue 32KB(0x00018000:0x0001ffff)
 msk0: <Marvell Technology Group Ltd. Yukon EC Ultra Id 0xb4 Rev 0x03> on mskc0
 msk0: bpf attached
 msk0: Ethernet address: 00:1a:4d:43:55:b0
 miibus0: <MII bus> on msk0
 e1000phy0: <Marvell 88E1149 Gigabit PHY> on miibus0
 e1000phy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseTX-FDX, auto
 ioapic0: routing intpin 17 (PCI IRQ 17) to vector 53
 mskc0: [MPSAFE]
 mskc0: [FAST]
 
 Now let try to reproduce a bug:
 
 typhoon# ifconfig msk0
 msk0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500
         options=1a<TXCSUM,VLAN_MTU,VLAN_HWTAGGING>
         ether 00:1a:4d:43:55:b0
         media: Ethernet autoselect (none)
         status: no carrier
 typhoon# ifconfig msk0 inet 212.40.39.230 netmask 255.255.255.252
 typhoon# ifconfig 
 msk0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> mtu 1500
         options=1a<TXCSUM,VLAN_MTU,VLAN_HWTAGGING>
         inet 212.40.39.230 netmask 0xfffffffc broadcast 212.40.39.231
         ether 00:1a:4d:43:55:b0
         media: Ethernet autoselect (none)
         status: no carrier
 
 	- Plug in FastEthernet cable:
 
 typhoon# ifconfig msk0
 msk0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> mtu 1500
         options=1a<TXCSUM,VLAN_MTU,VLAN_HWTAGGING>
         inet 212.40.39.230 netmask 0xfffffffc broadcast 212.40.39.231
         ether 00:1a:4d:43:55:b0
         media: Ethernet autoselect (100baseTX <full-duplex>)
         status: active
 
 	- Check connectivity, add default route
 typhoon# ping 212.40.39.229
 PING 212.40.39.229 (212.40.39.229): 56 data bytes
 64 bytes from 212.40.39.229: icmp_seq=0 ttl=255 time=0.562 ms
 64 bytes from 212.40.39.229: icmp_seq=1 ttl=255 time=0.674 ms
 ^C
 --- 212.40.39.229 ping statistics ---
 2 packets transmitted, 2 packets received, 0% packet loss
 round-trip min/avg/max/stddev = 0.562/0.618/0.674/0.056 ms
 
 	- Make some traffic. Let's ssh from remote host:
 remote-host# ssh 212.40.39.230
 ssh 212.40.39.230
 The authenticity of host '212.40.39.230 (212.40.39.230)' can't be established.
 DSA key fingerprint is fb:11:8c:a4:ce:70:14:3b:1c:0c:ab:db:86:c9:cd:1b.
 Are you sure you want to continue connecting (yes/no)? yes
 Warning: Permanently added '212.40.39.230' (DSA) to the list of known hosts.
 Password:
 Password:
 
 That's all. Connections stalls.
 
 Output on the console:
 mskc0: Tx descriptor error
 mskc0: Tx descriptor error
 mskc0: Tx descriptor error
 mskc0: Tx descriptor error
 mskc0: Tx descriptor error
 mskc0: Tx descriptor error
 msk0: watchdog timeout
 msk0: link state changed to DOWN
 msk0: link state changed to UP
 
 Status of msk0 is active and it seems that there is some traffic:
 typhoon# tcpdump -ni msk0
 tcpdump: verbose output suppressed, use -v or -vv for full protocol decode
 listening on msk0, link-type EN10MB (Ethernet), capture size 68 bytes
 10:42:53.627055 
 10:42:57.002861 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 0, length 64
 10:42:57.002885 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 0, length 64
 10:42:58.002948 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 1, length 64
 10:42:58.002966 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 1, length 64
 10:42:59.003837 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 2, length 64
 10:42:59.003848 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 2, length 64
 10:43:00.005792 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 3, length 64
 10:43:00.005802 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 3, length 64
 10:43:01.005834 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 4, length 64
 10:43:01.005844 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 4, length 64
 10:43:02.006781 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 5, length 64
 10:43:02.006791 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 5, length 64
 10:43:03.007799 IP 212.40.34.43 > 212.40.39.230: ICMP echo request, id 55828, seq 6, length 64
 10:43:03.007809 IP 212.40.39.230 > 212.40.34.43: ICMP echo reply, id 55828, seq 6, length 64
 
 BUT! That ICMP packets does not reach remote host:
 rhost# ping 212.40.39.230
 PING 212.40.39.230 (212.40.39.230): 56 data bytes
 ^C
 --- 212.40.39.230 ping statistics ---
 76 packets transmitted, 0 packets received, 100% packet loss
 
 Now bring interface msk0 down/up and check connectivity from remote host:
 
 typhoon# ifconfig msk0 down
 typhoon# ifconfig msk0 up
 
 rhost# ping 212.40.39.230
 PING 212.40.39.230 (212.40.39.230): 56 data bytes
 64 bytes from 212.40.39.230: icmp_seq=0 ttl=63 time=2.330 ms
 64 bytes from 212.40.39.230: icmp_seq=1 ttl=63 time=0.644 ms
 64 bytes from 212.40.39.230: icmp_seq=2 ttl=63 time=0.777 ms
 64 bytes from 212.40.39.230: icmp_seq=3 ttl=63 time=0.470 ms
 
 Let's ssh again and the same problem - connection stalls with a couple
 of "mskc0: Tx descriptor error" errors on the console.
 
 ------------------------------------------------------------------------------
 
 Thank you!
 
 -- 
 Kind Regards,	Alexander Shikoff
 minotaur@crete.org.ua

From: Pyun YongHyeon <pyunyh@gmail.com>
To: Alexander Shikoff <minotaur@crete.org.ua>
Cc: yongari@FreeBSD.org, bug-followup@FreeBSD.org
Subject: Re: kern/114631: [msk] "Tx descriptor error" with Marvell Yukon
Date: Thu, 19 Jul 2007 11:36:28 +0900

 --fUYQa+Pmc3FrFX/N
 Content-Type: text/plain; charset=us-ascii
 Content-Disposition: inline
 
 On Wed, Jul 18, 2007 at 11:08:48AM +0300, Alexander Shikoff wrote:
  > On Wed, Jul 18, 2007 at 05:04:20AM +0000, yongari@FreeBSD.org wrote:
  > > Synopsis: [msk] "Tx descriptor error" with Marvell Yukon
  > > 
  > > State-Changed-From-To: open->feedback
  > > State-Changed-By: yongari
  > > State-Changed-When: Wed Jul 18 05:03:36 UTC 2007
  > > State-Changed-Why: 
  > > Would you show me verbosed boot message related with msk(4)?
  > > Btw, in order to remove route directly connected with network
  > > interface you may have to use "ifconfig msk0 inet delete".
  > >
  > > http://www.freebsd.org/cgi/query-pr.cgi?pr=114631
  > 
  > Before I put here a lot of output I would like to add a comment.
  > Bringing interface down removes route properly. That was my failure while
  > playing with same IP on different interfaces.
  > 
  > 
  > In my case if_msk is compiled into kernel by adding "device msk" into kernel 
  > config file. Additionally, my make.conf includes CPUTYPE?=pentium4.
  > 
  > Here is output got with boot_verbose="YES" and verbose_loading="YES" in
  > /boot/loader.conf. Here typhoon# is a host witn problematic msk-interface,
  > rhost# - remote host.
  > 
  > mskc0: <Marvell Yukon 88E8056 Gigabit Ethernet> port 0x7000-0x70ff mem 0xf1000000-0xf1003fff irq 17 at device 0.0
  >  on pci2
  > mskc0: Reserved 0x4000 bytes for rid 0x10 type 3 at 0xf1000000
  > mskc0: MSI count : 0
  > mskc0: RAM buffer size : 128KB
  > mskc0: Port 0 : Rx Queue 96KB(0x00000000:0x00017fff)
  > mskc0: Port 0 : Tx Queue 32KB(0x00018000:0x0001ffff)
  > msk0: <Marvell Technology Group Ltd. Yukon EC Ultra Id 0xb4 Rev 0x03> on mskc0
  > msk0: bpf attached
  > msk0: Ethernet address: 00:1a:4d:43:55:b0
  > miibus0: <MII bus> on msk0
  > e1000phy0: <Marvell 88E1149 Gigabit PHY> on miibus0
  > e1000phy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseTX-FDX, auto
  > ioapic0: routing intpin 17 (PCI IRQ 17) to vector 53
  > mskc0: [MPSAFE]
  > mskc0: [FAST]
  > 
 
 [...]
 
 Would you try attached patch? I don't have Yukon EC Ultra based
 hardware so I'm not sure that the patch will fix the issue.
 
 Thanks.
 -- 
 Regards,
 Pyun YongHyeon
 
 --fUYQa+Pmc3FrFX/N
 Content-Type: text/plain; charset=us-ascii
 Content-Disposition: attachment; filename="msk.ec.diff"
 
 --- if_msk.c.orig	2007-06-11 11:00:50.000000000 +0900
 +++ if_msk.c	2007-07-14 05:47:18.000000000 +0900
 @@ -913,7 +913,7 @@
  			error = EINVAL;
  			break;
  		}
 -		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
 +		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
  		    ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
  			error = EINVAL;
  			break;
 @@ -980,6 +980,16 @@
  			else
  				ifp->if_hwassist &= ~CSUM_TSO;
  		}
 +		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
 +		    sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 +			/*
 +			 * In Yukon EC Ultra, TSO & checksum offload is not
 +			 * supported for jumbo frame.
 +			 */
 +			ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
 +			ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
 +		}
 +
  		VLAN_CAPABILITIES(ifp);
  		MSK_IF_UNLOCK(sc_if);
  		break;
 @@ -1450,13 +1460,8 @@
  	 * compute the checksum? I think there is no reason to spend time to
  	 * make Rx checksum offload work on Yukon II hardware.
  	 */
 -	ifp->if_capabilities = IFCAP_TXCSUM;
 -	ifp->if_hwassist = MSK_CSUM_FEATURES;
 -	if (sc->msk_hw_id != CHIP_ID_YUKON_EC_U) {
 -		/* It seems Yukon EC Ultra doesn't support TSO. */
 -		ifp->if_capabilities |= IFCAP_TSO4;
 -		ifp->if_hwassist |= CSUM_TSO;
 -	}
 +	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
 +	ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
  	ifp->if_capenable = ifp->if_capabilities;
  	ifp->if_ioctl = msk_ioctl;
  	ifp->if_start = msk_start;
 @@ -1502,6 +1507,9 @@
  	 */
          ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
  
 +	sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
 +	    ETHER_VLAN_ENCAP_LEN;
 +
  	/*
  	 * Do miibus setup.
  	 */
 @@ -3625,6 +3633,15 @@
  
  	sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
  	    ETHER_VLAN_ENCAP_LEN;
 +	if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
 +	    sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 +		/*
 +		 * In Yukon EC Ultra, TSO & checksum offload is not
 +		 * supported for jumbo frame.
 +		 */
 +		ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
 +		ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
 +	}
  
  	/*
  	 * Initialize GMAC first.
 @@ -3715,27 +3732,25 @@
  	/* Configure hardware VLAN tag insertion/stripping. */
  	msk_setvlan(sc_if, ifp);
  
 -	/* XXX It seems STFW is requried for all cases. */
 -	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), TX_STFW_ENA);
 -
  	if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
  		/* Set Rx Pause threshould. */
  		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
  		    MSK_ECU_LLPP);
  		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
  		    MSK_ECU_ULPP);
 +		/*
 +		 * Set Tx GMAC FIFO Almost Empty Threshold.
 +		 */
 +		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
 +		    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
  		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
 -			/*
 -			 * Can't sure the following code is needed as Yukon
 -			 * Yukon EC Ultra may not support jumbo frames.
 -			 *
 -			 * Set Tx GMAC FIFO Almost Empty Threshold.
 -			 */
 -			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
 -			    MSK_ECU_AE_THR);
  			/* Disable Store & Forward mode for Tx. */
  			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_STFW_DIS);
 +			    TX_JUMBO_ENA | TX_STFW_DIS);
 +		} else {
 +			/* Enable Store & Forward mode for Tx. */
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_JUMBO_DIS | TX_STFW_ENA);
  		}
  	}
  
 --- if_mskreg.h.orig	2007-05-25 22:57:08.000000000 +0900
 +++ if_mskreg.h	2007-07-14 05:25:27.000000000 +0900
 @@ -1082,8 +1082,9 @@
  /* Threshold values for Yukon-EC Ultra */
  #define	MSK_ECU_ULPP	0x0080	/* Upper Pause Threshold (multiples of 8) */
  #define	MSK_ECU_LLPP	0x0060	/* Lower Pause Threshold (multiples of 8) */
 -#define	MSK_ECU_AE_THR	0x0180  /* Almost Empty Threshold */
 +#define	MSK_ECU_AE_THR	0x0070  /* Almost Empty Threshold */
  #define	MSK_ECU_TXFF_LEV	0x01a0	/* Tx BMU FIFO Level */
 +#define	MSK_ECU_JUMBO_WM	0x01
  
  #define MSK_BMU_RX_WM		0x600	/* BMU Rx Watermark */
  #define MSK_BMU_TX_WM		0x600	/* BMU Tx Watermark */
 @@ -1863,6 +1864,8 @@
  #define	TX_STFW_ENA	BIT_30	/* Enable Store & Forward (Yukon-EC Ultra) */
  #define TX_VLAN_TAG_ON	BIT_25	/* enable  VLAN tagging */
  #define TX_VLAN_TAG_OFF	BIT_24	/* disable VLAN tagging */
 +#define	TX_JUMBO_ENA	BIT_23	/* Enable Jumbo Mode (Yukon-EC Ultra) */
 +#define	TX_JUMBO_DIS	BIT_22	/* Disable Jumbo Mode (Yukon-EC Ultra) */
  #define GMF_WSP_TST_ON	BIT_18	/* Write Shadow Pointer Test On */
  #define GMF_WSP_TST_OFF	BIT_17	/* Write Shadow Pointer Test Off */
  #define GMF_WSP_STEP	BIT_16	/* Write Shadow Pointer Step/Increment */
 @@ -2384,6 +2387,7 @@
  	struct task		msk_link_task;
  	struct task		msk_tx_task;
  	int			msk_if_flags;
 +	int			msk_jumbo_disable;
  	int			msk_detach;
  	uint16_t		msk_vtag;	/* VLAN tag id. */
  	SLIST_HEAD(__msk_jfreehead, msk_jpool_entry)	msk_jfree_listhead;
 
 --fUYQa+Pmc3FrFX/N--

From: Alexander Shikoff <minotaur@crete.org.ua>
To: Pyun YongHyeon <pyunyh@gmail.com>
Cc: yongari@FreeBSD.org, bug-followup@FreeBSD.org
Subject: Re: kern/114631: [msk] "Tx descriptor error" with Marvell Yukon
Date: Thu, 19 Jul 2007 14:04:01 +0300

 On Thu, Jul 19, 2007 at 11:36:28AM +0900, Pyun YongHyeon wrote:
 > --- if_msk.c.orig	2007-06-11 11:00:50.000000000 +0900
 > +++ if_msk.c	2007-07-14 05:47:18.000000000 +0900
 > @@ -913,7 +913,7 @@
 >  			error = EINVAL;
 >  			break;
 >  		}
 > -		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
 > +		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
 >  		    ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
 >  			error = EINVAL;
 >  			break;
 > @@ -980,6 +980,16 @@
 >  			else
 >  				ifp->if_hwassist &= ~CSUM_TSO;
 >  		}
 > +		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
 > +		    sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 > +			/*
 > +			 * In Yukon EC Ultra, TSO & checksum offload is not
 > +			 * supported for jumbo frame.
 > +			 */
 > +			ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
 > +			ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
 > +		}
 > +
 >  		VLAN_CAPABILITIES(ifp);
 >  		MSK_IF_UNLOCK(sc_if);
 >  		break;
 > @@ -1450,13 +1460,8 @@
 >  	 * compute the checksum? I think there is no reason to spend time to
 >  	 * make Rx checksum offload work on Yukon II hardware.
 >  	 */
 > -	ifp->if_capabilities = IFCAP_TXCSUM;
 > -	ifp->if_hwassist = MSK_CSUM_FEATURES;
 > -	if (sc->msk_hw_id != CHIP_ID_YUKON_EC_U) {
 > -		/* It seems Yukon EC Ultra doesn't support TSO. */
 > -		ifp->if_capabilities |= IFCAP_TSO4;
 > -		ifp->if_hwassist |= CSUM_TSO;
 > -	}
 > +	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
 > +	ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
 >  	ifp->if_capenable = ifp->if_capabilities;
 >  	ifp->if_ioctl = msk_ioctl;
 >  	ifp->if_start = msk_start;
 > @@ -1502,6 +1507,9 @@
 >  	 */
 >          ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 >  
 > +	sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
 > +	    ETHER_VLAN_ENCAP_LEN;
 > +
 >  	/*
 >  	 * Do miibus setup.
 >  	 */
 > @@ -3625,6 +3633,15 @@
 >  
 >  	sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN +
 >  	    ETHER_VLAN_ENCAP_LEN;
 > +	if (sc_if->msk_framesize > MSK_MAX_FRAMELEN &&
 > +	    sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 > +		/*
 > +		 * In Yukon EC Ultra, TSO & checksum offload is not
 > +		 * supported for jumbo frame.
 > +		 */
 > +		ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
 > +		ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
 > +	}
 >  
 >  	/*
 >  	 * Initialize GMAC first.
 > @@ -3715,27 +3732,25 @@
 >  	/* Configure hardware VLAN tag insertion/stripping. */
 >  	msk_setvlan(sc_if, ifp);
 >  
 > -	/* XXX It seems STFW is requried for all cases. */
 > -	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), TX_STFW_ENA);
 > -
 >  	if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 >  		/* Set Rx Pause threshould. */
 >  		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
 >  		    MSK_ECU_LLPP);
 >  		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
 >  		    MSK_ECU_ULPP);
 > +		/*
 > +		 * Set Tx GMAC FIFO Almost Empty Threshold.
 > +		 */
 > +		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
 > +		    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
 >  		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
 > -			/*
 > -			 * Can't sure the following code is needed as Yukon
 > -			 * Yukon EC Ultra may not support jumbo frames.
 > -			 *
 > -			 * Set Tx GMAC FIFO Almost Empty Threshold.
 > -			 */
 > -			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
 > -			    MSK_ECU_AE_THR);
 >  			/* Disable Store & Forward mode for Tx. */
 >  			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 > -			    TX_STFW_DIS);
 > +			    TX_JUMBO_ENA | TX_STFW_DIS);
 > +		} else {
 > +			/* Enable Store & Forward mode for Tx. */
 > +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 > +			    TX_JUMBO_DIS | TX_STFW_ENA);
 >  		}
 >  	}
 >  
 > --- if_mskreg.h.orig	2007-05-25 22:57:08.000000000 +0900
 > +++ if_mskreg.h	2007-07-14 05:25:27.000000000 +0900
 > @@ -1082,8 +1082,9 @@
 >  /* Threshold values for Yukon-EC Ultra */
 >  #define	MSK_ECU_ULPP	0x0080	/* Upper Pause Threshold (multiples of 8) */
 >  #define	MSK_ECU_LLPP	0x0060	/* Lower Pause Threshold (multiples of 8) */
 > -#define	MSK_ECU_AE_THR	0x0180  /* Almost Empty Threshold */
 > +#define	MSK_ECU_AE_THR	0x0070  /* Almost Empty Threshold */
 >  #define	MSK_ECU_TXFF_LEV	0x01a0	/* Tx BMU FIFO Level */
 > +#define	MSK_ECU_JUMBO_WM	0x01
 >  
 >  #define MSK_BMU_RX_WM		0x600	/* BMU Rx Watermark */
 >  #define MSK_BMU_TX_WM		0x600	/* BMU Tx Watermark */
 > @@ -1863,6 +1864,8 @@
 >  #define	TX_STFW_ENA	BIT_30	/* Enable Store & Forward (Yukon-EC Ultra) */
 >  #define TX_VLAN_TAG_ON	BIT_25	/* enable  VLAN tagging */
 >  #define TX_VLAN_TAG_OFF	BIT_24	/* disable VLAN tagging */
 > +#define	TX_JUMBO_ENA	BIT_23	/* Enable Jumbo Mode (Yukon-EC Ultra) */
 > +#define	TX_JUMBO_DIS	BIT_22	/* Disable Jumbo Mode (Yukon-EC Ultra) */
 >  #define GMF_WSP_TST_ON	BIT_18	/* Write Shadow Pointer Test On */
 >  #define GMF_WSP_TST_OFF	BIT_17	/* Write Shadow Pointer Test Off */
 >  #define GMF_WSP_STEP	BIT_16	/* Write Shadow Pointer Step/Increment */
 > @@ -2384,6 +2387,7 @@
 >  	struct task		msk_link_task;
 >  	struct task		msk_tx_task;
 >  	int			msk_if_flags;
 > +	int			msk_jumbo_disable;
 >  	int			msk_detach;
 >  	uint16_t		msk_vtag;	/* VLAN tag id. */
 >  	SLIST_HEAD(__msk_jfreehead, msk_jpool_entry)	msk_jfree_listhead;
 
 Applying this patch to if_msk.c rev. 1.11.2.6 fails:
 # patch < msk.ec.diff 
 Hmm...  Looks like a unified diff to me...
 The text leading up to this was:
 --------------------------
 |--- if_msk.c.orig      2007-06-11 11:00:50.000000000 +0900
 |+++ if_msk.c   2007-07-14 05:47:18.000000000 +0900
 --------------------------
 Patching file if_msk.c using Plan A...
 Hunk #1 succeeded at 906 (offset -7 lines).
 Hunk #2 succeeded at 973 (offset -7 lines).
 Hunk #3 failed at 1453.
 Hunk #4 succeeded at 1515 (offset 8 lines).
 Hunk #5 succeeded at 3688 (offset 55 lines).
 Hunk #6 succeeded at 3740 (offset 8 lines).
 1 out of 6 hunks failed--saving rejects to if_msk.c.rej
 
 I've edited if_msk.c a little near line 1453 to get this patch applying
 correctly (I've removed comment and #if #endif).
 
 After recompiling the kernel issue does not dissapear. But now
 connection freezes without "Tx descriptor error".
 Now there is only "msk0: watchdog timeout" errors on the console.
 
 -- 
 Kind Regards,	Alexander Shikoff
 minotaur@crete.org.ua

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/114631: commit references a PR
Date: Sun, 14 Mar 2010 23:24:11 +0000 (UTC)

 Author: yongari
 Date: Sun Mar 14 23:23:57 2010
 New Revision: 205161
 URL: http://svn.freebsd.org/changeset/base/205161
 
 Log:
   It seems PCI_OUR_REG_[1-5] registers are not mapped on PCI
   configuration space on Yukon Ultra(88E8056) such that accesses to
   these registers were NOPs which in turn make msk(4) instable on
   this controller. Use indirect access method to access
   PCI_OUR_REG_[1-5] registers. This should fix a long standing
   instability bug which prevented msk(4) working on Yukon Ultra.
   Special thanks to koitsu who gave me remote access to his system.
   
   PR:	kern/114631, kern/116853
   MFC after:	1 week
 
 Modified:
   head/sys/dev/msk/if_msk.c
 
 Modified: head/sys/dev/msk/if_msk.c
 ==============================================================================
 --- head/sys/dev/msk/if_msk.c	Sun Mar 14 22:38:18 2010	(r205160)
 +++ head/sys/dev/msk/if_msk.c	Sun Mar 14 23:23:57 2010	(r205161)
 @@ -1212,7 +1212,7 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 +		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
  		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
 @@ -1223,7 +1223,7 @@ msk_phy_power(struct msk_softc *sc, int 
  			}
  		}
  		/* Release PHY from PowerDown/COMA mode. */
 -		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
  		switch (sc->msk_hw_id) {
  		case CHIP_ID_YUKON_EC_U:
  		case CHIP_ID_YUKON_EX:
 @@ -1232,16 +1232,16 @@ msk_phy_power(struct msk_softc *sc, int 
  			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
  
  			/* Enable all clocks. */
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
 -			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
  			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
  			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
 -			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 +			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
  			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4);
 -			pci_write_config(sc->msk_dev, PCI_CFG_REG_1, 0, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1262,7 +1262,7 @@ msk_phy_power(struct msk_softc *sc, int 
  		}
  		break;
  	case MSK_PHY_POWERDOWN:
 -		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 +		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
  		val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
  		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
 @@ -1270,7 +1270,7 @@ msk_phy_power(struct msk_softc *sc, int 
  			if (sc->msk_num_port > 1)
  				val &= ~PCI_Y2_PHY2_COMA;
  		}
 -		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
  
  		val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  		      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
 _______________________________________________
 svn-src-all@freebsd.org mailing list
 http://lists.freebsd.org/mailman/listinfo/svn-src-all
 To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
 

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/114631: commit references a PR
Date: Wed, 24 Mar 2010 17:37:10 +0000 (UTC)

 Author: yongari
 Date: Wed Mar 24 17:36:56 2010
 New Revision: 205617
 URL: http://svn.freebsd.org/changeset/base/205617
 
 Log:
   MFC r205161:
     It seems PCI_OUR_REG_[1-5] registers are not mapped on PCI
     configuration space on Yukon Ultra(88E8056) such that accesses to
     these registers were NOPs which in turn make msk(4) instable on
     this controller. Use indirect access method to access
     PCI_OUR_REG_[1-5] registers. This should fix a long standing
     instability bug which prevented msk(4) working on Yukon Ultra.
     Special thanks to koitsu who gave me remote access to his system.
   
     PR:	kern/114631, kern/116853
 
 Modified:
   stable/8/sys/dev/msk/if_msk.c
 Directory Properties:
   stable/8/sys/   (props changed)
   stable/8/sys/amd64/include/xen/   (props changed)
   stable/8/sys/cddl/contrib/opensolaris/   (props changed)
   stable/8/sys/contrib/dev/acpica/   (props changed)
   stable/8/sys/contrib/pf/   (props changed)
   stable/8/sys/dev/xen/xenpci/   (props changed)
   stable/8/sys/net/   (props changed)
   stable/8/sys/netinet/ipfw/   (props changed)
 
 Modified: stable/8/sys/dev/msk/if_msk.c
 ==============================================================================
 --- stable/8/sys/dev/msk/if_msk.c	Wed Mar 24 17:32:20 2010	(r205616)
 +++ stable/8/sys/dev/msk/if_msk.c	Wed Mar 24 17:36:56 2010	(r205617)
 @@ -1125,7 +1125,7 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 +		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
  		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
 @@ -1136,7 +1136,7 @@ msk_phy_power(struct msk_softc *sc, int 
  			}
  		}
  		/* Release PHY from PowerDown/COMA mode. */
 -		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
  		switch (sc->msk_hw_id) {
  		case CHIP_ID_YUKON_EC_U:
  		case CHIP_ID_YUKON_EX:
 @@ -1145,16 +1145,16 @@ msk_phy_power(struct msk_softc *sc, int 
  			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
  
  			/* Enable all clocks. */
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
 -			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
  			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
  			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
 -			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 +			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
  			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4);
 -			pci_write_config(sc->msk_dev, PCI_CFG_REG_1, 0, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1175,7 +1175,7 @@ msk_phy_power(struct msk_softc *sc, int 
  		}
  		break;
  	case MSK_PHY_POWERDOWN:
 -		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 +		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
  		val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
  		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
 @@ -1183,7 +1183,7 @@ msk_phy_power(struct msk_softc *sc, int 
  			if (sc->msk_num_port > 1)
  				val &= ~PCI_Y2_PHY2_COMA;
  		}
 -		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
  
  		val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  		      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
 _______________________________________________
 svn-src-all@freebsd.org mailing list
 http://lists.freebsd.org/mailman/listinfo/svn-src-all
 To unsubscribe, send any mail to "svn-src-all-unsubscribe@freebsd.org"
 

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/114631: commit references a PR
Date: Wed, 24 Mar 2010 17:38:21 +0000 (UTC)

 Author: yongari
 Date: Wed Mar 24 17:38:08 2010
 New Revision: 205618
 URL: http://svn.freebsd.org/changeset/base/205618
 
 Log:
   MFC r205161:
     It seems PCI_OUR_REG_[1-5] registers are not mapped on PCI
     configuration space on Yukon Ultra(88E8056) such that accesses to
     these registers were NOPs which in turn make msk(4) instable on
     this controller. Use indirect access method to access
     PCI_OUR_REG_[1-5] registers. This should fix a long standing
     instability bug which prevented msk(4) working on Yukon Ultra.
     Special thanks to koitsu who gave me remote access to his system.
   
     PR:	kern/114631, kern/116853
 
 Modified:
   stable/7/sys/dev/msk/if_msk.c
 Directory Properties:
   stable/7/sys/   (props changed)
   stable/7/sys/cddl/contrib/opensolaris/   (props changed)
   stable/7/sys/contrib/dev/acpica/   (props changed)
   stable/7/sys/contrib/pf/   (props changed)
 
 Modified: stable/7/sys/dev/msk/if_msk.c
 ==============================================================================
 --- stable/7/sys/dev/msk/if_msk.c	Wed Mar 24 17:36:56 2010	(r205617)
 +++ stable/7/sys/dev/msk/if_msk.c	Wed Mar 24 17:38:08 2010	(r205618)
 @@ -1125,7 +1125,7 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 +		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
  		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
 @@ -1136,7 +1136,7 @@ msk_phy_power(struct msk_softc *sc, int 
  			}
  		}
  		/* Release PHY from PowerDown/COMA mode. */
 -		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
  		switch (sc->msk_hw_id) {
  		case CHIP_ID_YUKON_EC_U:
  		case CHIP_ID_YUKON_EX:
 @@ -1145,16 +1145,16 @@ msk_phy_power(struct msk_softc *sc, int 
  			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
  
  			/* Enable all clocks. */
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
 -			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
  			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
  			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
 -			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 +			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
  			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4);
 -			pci_write_config(sc->msk_dev, PCI_CFG_REG_1, 0, 4);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1175,7 +1175,7 @@ msk_phy_power(struct msk_softc *sc, int 
  		}
  		break;
  	case MSK_PHY_POWERDOWN:
 -		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 +		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
  		val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
  		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
 @@ -1183,7 +1183,7 @@ msk_phy_power(struct msk_softc *sc, int 
  			if (sc->msk_num_port > 1)
  				val &= ~PCI_Y2_PHY2_COMA;
  		}
 -		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
  
  		val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  		      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
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From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/114631: commit references a PR
Date: Wed, 22 Jun 2011 01:43:13 +0000 (UTC)

 Author: yongari
 Date: Wed Jun 22 01:42:52 2011
 New Revision: 223396
 URL: http://svn.freebsd.org/changeset/base/223396
 
 Log:
   MFC r222219,222221,222223,222226-222227,222231,222516:
     Merge all relevant changes from HEAD to fix long standing
     instability issues of msk(4).  To get desired effect of this
     merge, cold restarting is required because incorrectly programmed
     registers are not reset to default value.
     PR:	kern/114631, kern/116853, kern/139093, kern/144206,
   	kern/147824, kern/151169, kern/154591, kern/155636,
   	kern/156493
   
   r222219:
     Do not blindly clear entire GPHY control register. It seems some
     bits of the register is used for other purposes such that clearing
     these bits resulted in unexpected results such as corrupted RX
     frames or missing LE status updates.  For old controllers like
     Yukon EC it had no effect but it caused all kind of troubles on
     Yukon Supreme.
     This change shall improve stability of controllers like Yukon
     Ultra, Ultra2, Extreme, Optima and Supreme.
   
   r222221:
     Rework store and forward configuration of TX MAC FIFO. Basically it
     enables store and forward mode except for jumbo frame on Yukon
     Ultra.
   
   r222223:
     Do not configure RAM registers for controllers that do not have
     them.  These registers are defined only for Yukon XL, Yukon EC and
     Yukon FE.
   
   r222226:
     Make sure to enable all clocks before accessing registers.
     Releasing PHY from power down/COMA is done after enabling all
     clocks. While I'm here remove unnecessary controller reset.
   
   r222227:
     Do not touch ASF related register for controllers that do not have
     these registers. Also disable Watchdog of ASF microcontroller.
   
   r222231:
     When MTU is changed, check whether driver should be reinitialized or
     not.  If reinitialized is required, clear driver running flag.
   
   r222516:
     Correctly check MAC running status before disabling TX/RX MACs.
 
 Modified:
   stable/8/sys/dev/msk/if_msk.c
   stable/8/sys/dev/msk/if_mskreg.h
 Directory Properties:
   stable/8/sys/   (props changed)
   stable/8/sys/amd64/include/xen/   (props changed)
   stable/8/sys/cddl/contrib/opensolaris/   (props changed)
   stable/8/sys/contrib/dev/acpica/   (props changed)
   stable/8/sys/contrib/pf/   (props changed)
 
 Modified: stable/8/sys/dev/msk/if_msk.c
 ==============================================================================
 --- stable/8/sys/dev/msk/if_msk.c	Wed Jun 22 00:49:24 2011	(r223395)
 +++ stable/8/sys/dev/msk/if_msk.c	Wed Jun 22 01:42:52 2011	(r223396)
 @@ -562,7 +562,7 @@ msk_miibus_statchg(device_t dev)
  		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
  		/* Disable Rx/Tx MAC. */
  		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
 -		if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
 +		if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
  			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
  			/* Read again to ensure writing. */
 @@ -1030,7 +1030,10 @@ msk_ioctl(struct ifnet *ifp, u_long comm
  				}
  			}
  			ifp->if_mtu = ifr->ifr_mtu;
 -			msk_init_locked(sc_if);
 +			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 +				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 +				msk_init_locked(sc_if);
 +			}
  		}
  		MSK_IF_UNLOCK(sc_if);
  		break;
 @@ -1212,37 +1215,30 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 -		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 +		our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 +		our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
  				/* Deassert Low Power for 1st PHY. */
 -				val |= PCI_Y2_PHY1_COMA;
 +				our |= PCI_Y2_PHY1_COMA;
  				if (sc->msk_num_port > 1)
 -					val |= PCI_Y2_PHY2_COMA;
 +					our |= PCI_Y2_PHY2_COMA;
  			}
  		}
 -		/* Release PHY from PowerDown/COMA mode. */
 -		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
 -		switch (sc->msk_hw_id) {
 -		case CHIP_ID_YUKON_EC_U:
 -		case CHIP_ID_YUKON_EX:
 -		case CHIP_ID_YUKON_FE_P:
 -		case CHIP_ID_YUKON_UL_2:
 -		case CHIP_ID_YUKON_OPT:
 -			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 -
 -			/* Enable all clocks. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 -			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
 -			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 +			val &= (PCI_FORCE_ASPM_REQUEST |
 +			    PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
 +			    PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 -			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 +			val &= PCI_CTL_TIM_VMAIN_AV_MSK;
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
  			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
 +			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1251,10 +1247,10 @@ msk_phy_power(struct msk_softc *sc, int 
  			val |= GLB_GPIO_STAT_RACE_DIS;
  			CSR_WRITE_4(sc, B2_GP_IO, val);
  			CSR_READ_4(sc, B2_GP_IO);
 -			break;
 -		default:
 -			break;
  		}
 +		/* Release PHY from PowerDown/COMA mode. */
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
 +
  		for (i = 0; i < sc->msk_num_port; i++) {
  			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
  			    GMLC_RST_SET);
 @@ -1300,28 +1296,33 @@ mskc_reset(struct msk_softc *sc)
  	bus_addr_t addr;
  	uint16_t status;
  	uint32_t val;
 -	int i;
 -
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	int i, initram;
  
  	/* Disable ASF. */
 -	if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
 -		status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 -		/* Clear AHB bridge & microcontroller reset. */
 -		status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 -		    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 -		/* Clear ASF microcontroller state. */
 -		status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 -		CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 -	} else
 -		CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 -	CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 -
 -	/*
 -	 * Since we disabled ASF, S/W reset is required for Power Management.
 -	 */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
 +	    sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +			status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 +			/* Clear AHB bridge & microcontroller reset. */
 +			status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 +			    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 +			/* Clear ASF microcontroller state. */
 +			status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 +			status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
 +			CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +		} else
 +			CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 +		CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 +		/*
 +		 * Since we disabled ASF, S/W reset is required for
 +		 * Power Management.
 +		 */
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	}
  
  	/* Clear all error bits in the PCI status register. */
  	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
 @@ -1362,8 +1363,8 @@ mskc_reset(struct msk_softc *sc)
  	/* Reset GPHY/GMAC Control */
  	for (i = 0; i < sc->msk_num_port; i++) {
  		/* GPHY Control reset. */
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
  		/* GMAC Control reset. */
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
 @@ -1396,8 +1397,14 @@ mskc_reset(struct msk_softc *sc)
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  
 +	initram = 0;
 +	if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_EC ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_FE)
 +		initram++;
 +
  	/* Configure timeout values. */
 -	for (i = 0; i < sc->msk_num_port; i++) {
 +	for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
 @@ -1708,6 +1715,9 @@ mskc_attach(device_t dev)
  		}
  	}
  
 +	/* Enable all clocks before accessing any registers. */
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +
  	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
  	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
 @@ -1748,9 +1758,6 @@ mskc_attach(device_t dev)
  	resource_int_value(device_get_name(dev), device_get_unit(dev),
  	    "int_holdoff", &sc->msk_int_holdoff);
  
 -	/* Soft reset. */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
  	/* Check number of MACs. */
  	sc->msk_num_port = 1;
 @@ -2964,6 +2971,7 @@ mskc_resume(device_t dev)
  
  	MSK_LOCK(sc);
  
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
  	mskc_reset(sc);
  	for (i = 0; i < sc->msk_num_port; i++) {
  		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
 @@ -3655,37 +3663,24 @@ msk_set_tx_stfwd(struct msk_if_softc *sc
  
  	ifp = sc_if->msk_ifp;
  	sc = sc_if->msk_softc;
 -	switch (sc->msk_hw_id) {
 -	case CHIP_ID_YUKON_EX:
 -		if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
 -			goto yukon_ex_workaround;
 -		if (ifp->if_mtu > ETHERMTU)
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_ENA);
 -		else
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 -		break;
 -	default:
 -yukon_ex_workaround:
 +	if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
 +	    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
 +	    sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
 +		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +		    TX_STFW_ENA);
 +	} else {
  		if (ifp->if_mtu > ETHERMTU) {
  			/* Set Tx GMAC FIFO Almost Empty Threshold. */
  			CSR_WRITE_4(sc,
  			    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
  			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
  			/* Disable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_DIS);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_DIS);
  		} else {
 -			/* Enable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_ENA);
  		}
 -		break;
  	}
  }
  
 
 Modified: stable/8/sys/dev/msk/if_mskreg.h
 ==============================================================================
 --- stable/8/sys/dev/msk/if_mskreg.h	Wed Jun 22 00:49:24 2011	(r223395)
 +++ stable/8/sys/dev/msk/if_mskreg.h	Wed Jun 22 01:42:52 2011	(r223396)
 @@ -677,6 +677,7 @@
  /* ASF Subsystem Registers (Yukon-2 only) */
  #define B28_Y2_SMB_CONFIG	0x0e40	/* 32 bit ASF SMBus Config Register */
  #define B28_Y2_SMB_CSD_REG	0x0e44	/* 32 bit ASF SMB Control/Status/Data */
 +#define B28_Y2_CPU_WDOG		0x0e48	/* 32 bit Watchdog Register */
  #define B28_Y2_ASF_IRQ_V_BASE	0x0e60	/* 32 bit ASF IRQ Vector Base */
  #define B28_Y2_ASF_STAT_CMD	0x0e68	/* 32 bit ASF Status and Command Reg */
  #define B28_Y2_ASF_HCU_CCSR	0x0e68	/* 32 bit ASF HCU CCSR (Yukon EX) */
 _______________________________________________
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From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: kern/114631: commit references a PR
Date: Wed, 22 Jun 2011 01:44:18 +0000 (UTC)

 Author: yongari
 Date: Wed Jun 22 01:44:09 2011
 New Revision: 223397
 URL: http://svn.freebsd.org/changeset/base/223397
 
 Log:
   MFC r222219,222221,222223,222226-222227,222231,222516:
     Merge all relevant changes from HEAD to fix long standing
     instability issues of msk(4).  To get desired effect of this
     merge, cold restarting is required because incorrectly programmed
     registers are not reset to default value.
     PR:	kern/114631, kern/116853, kern/139093, kern/144206,
   	kern/147824, kern/151169, kern/154591, kern/155636,
   	kern/156493
   
   r222219:
     Do not blindly clear entire GPHY control register. It seems some
     bits of the register is used for other purposes such that clearing
     these bits resulted in unexpected results such as corrupted RX
     frames or missing LE status updates.  For old controllers like
     Yukon EC it had no effect but it caused all kind of troubles on
     Yukon Supreme.
     This change shall improve stability of controllers like Yukon
     Ultra, Ultra2, Extreme, Optima and Supreme.
   
   r222221:
     Rework store and forward configuration of TX MAC FIFO. Basically it
     enables store and forward mode except for jumbo frame on Yukon
     Ultra.
   
   r222223:
     Do not configure RAM registers for controllers that do not have
     them.  These registers are defined only for Yukon XL, Yukon EC and
     Yukon FE.
   
   r222226:
     Make sure to enable all clocks before accessing registers.
     Releasing PHY from power down/COMA is done after enabling all
     clocks. While I'm here remove unnecessary controller reset.
   
   r222227:
     Do not touch ASF related register for controllers that do not have
     these registers. Also disable Watchdog of ASF microcontroller.
   
   r222231:
     When MTU is changed, check whether driver should be reinitialized or
     not.  If reinitialized is required, clear driver running flag.
   
   r222516:
     Correctly check MAC running status before disabling TX/RX MACs.
 
 Modified:
   stable/7/sys/dev/msk/if_msk.c
   stable/7/sys/dev/msk/if_mskreg.h
 Directory Properties:
   stable/7/sys/   (props changed)
   stable/7/sys/cddl/contrib/opensolaris/   (props changed)
   stable/7/sys/contrib/dev/acpica/   (props changed)
   stable/7/sys/contrib/pf/   (props changed)
 
 Modified: stable/7/sys/dev/msk/if_msk.c
 ==============================================================================
 --- stable/7/sys/dev/msk/if_msk.c	Wed Jun 22 01:42:52 2011	(r223396)
 +++ stable/7/sys/dev/msk/if_msk.c	Wed Jun 22 01:44:09 2011	(r223397)
 @@ -562,7 +562,7 @@ msk_miibus_statchg(device_t dev)
  		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
  		/* Disable Rx/Tx MAC. */
  		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
 -		if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
 +		if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
  			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
  			/* Read again to ensure writing. */
 @@ -1030,7 +1030,10 @@ msk_ioctl(struct ifnet *ifp, u_long comm
  				}
  			}
  			ifp->if_mtu = ifr->ifr_mtu;
 -			msk_init_locked(sc_if);
 +			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 +				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 +				msk_init_locked(sc_if);
 +			}
  		}
  		MSK_IF_UNLOCK(sc_if);
  		break;
 @@ -1212,37 +1215,30 @@ msk_phy_power(struct msk_softc *sc, int 
  		 */
  		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
  
 -		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 -		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
 +		our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
 +		our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
  		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
  			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
  				/* Deassert Low Power for 1st PHY. */
 -				val |= PCI_Y2_PHY1_COMA;
 +				our |= PCI_Y2_PHY1_COMA;
  				if (sc->msk_num_port > 1)
 -					val |= PCI_Y2_PHY2_COMA;
 +					our |= PCI_Y2_PHY2_COMA;
  			}
  		}
 -		/* Release PHY from PowerDown/COMA mode. */
 -		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
 -		switch (sc->msk_hw_id) {
 -		case CHIP_ID_YUKON_EC_U:
 -		case CHIP_ID_YUKON_EX:
 -		case CHIP_ID_YUKON_FE_P:
 -		case CHIP_ID_YUKON_UL_2:
 -		case CHIP_ID_YUKON_OPT:
 -			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 -
 -			/* Enable all clocks. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 -			our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN|
 -			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
 +			val &= (PCI_FORCE_ASPM_REQUEST |
 +			    PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
 +			    PCI_ASPM_CLKRUN_REQUEST);
  			/* Set all bits to 0 except bits 15..12. */
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our);
 -			our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 -			our &= PCI_CTL_TIM_VMAIN_AV_MSK;
 -			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our);
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
 +			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
 +			val &= PCI_CTL_TIM_VMAIN_AV_MSK;
 +			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
  			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
 +			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
  			/*
  			 * Disable status race, workaround for
  			 * Yukon EC Ultra & Yukon EX.
 @@ -1251,10 +1247,10 @@ msk_phy_power(struct msk_softc *sc, int 
  			val |= GLB_GPIO_STAT_RACE_DIS;
  			CSR_WRITE_4(sc, B2_GP_IO, val);
  			CSR_READ_4(sc, B2_GP_IO);
 -			break;
 -		default:
 -			break;
  		}
 +		/* Release PHY from PowerDown/COMA mode. */
 +		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
 +
  		for (i = 0; i < sc->msk_num_port; i++) {
  			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
  			    GMLC_RST_SET);
 @@ -1300,28 +1296,33 @@ mskc_reset(struct msk_softc *sc)
  	bus_addr_t addr;
  	uint16_t status;
  	uint32_t val;
 -	int i;
 -
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	int i, initram;
  
  	/* Disable ASF. */
 -	if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
 -		status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 -		/* Clear AHB bridge & microcontroller reset. */
 -		status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 -		    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 -		/* Clear ASF microcontroller state. */
 -		status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 -		CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 -	} else
 -		CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 -	CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 -
 -	/*
 -	 * Since we disabled ASF, S/W reset is required for Power Management.
 -	 */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
 +	    sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
 +		if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
 +		    sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +			status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
 +			/* Clear AHB bridge & microcontroller reset. */
 +			status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
 +			    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
 +			/* Clear ASF microcontroller state. */
 +			status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
 +			status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
 +			CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
 +			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
 +		} else
 +			CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
 +		CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
 +		/*
 +		 * Since we disabled ASF, S/W reset is required for
 +		 * Power Management.
 +		 */
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 +		CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
 +	}
  
  	/* Clear all error bits in the PCI status register. */
  	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
 @@ -1362,8 +1363,8 @@ mskc_reset(struct msk_softc *sc)
  	/* Reset GPHY/GMAC Control */
  	for (i = 0; i < sc->msk_num_port; i++) {
  		/* GPHY Control reset. */
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 -		CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
 +		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
  		/* GMAC Control reset. */
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
  		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
 @@ -1396,8 +1397,14 @@ mskc_reset(struct msk_softc *sc)
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  
 +	initram = 0;
 +	if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_EC ||
 +	    sc->msk_hw_id == CHIP_ID_YUKON_FE)
 +		initram++;
 +
  	/* Configure timeout values. */
 -	for (i = 0; i < sc->msk_num_port; i++) {
 +	for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
  		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
 @@ -1708,6 +1715,9 @@ mskc_attach(device_t dev)
  		}
  	}
  
 +	/* Enable all clocks before accessing any registers. */
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
 +
  	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
  	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
 @@ -1748,9 +1758,6 @@ mskc_attach(device_t dev)
  	resource_int_value(device_get_name(dev), device_get_unit(dev),
  	    "int_holdoff", &sc->msk_int_holdoff);
  
 -	/* Soft reset. */
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
 -	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
  	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
  	/* Check number of MACs. */
  	sc->msk_num_port = 1;
 @@ -2964,6 +2971,7 @@ mskc_resume(device_t dev)
  
  	MSK_LOCK(sc);
  
 +	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
  	mskc_reset(sc);
  	for (i = 0; i < sc->msk_num_port; i++) {
  		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
 @@ -3655,37 +3663,24 @@ msk_set_tx_stfwd(struct msk_if_softc *sc
  
  	ifp = sc_if->msk_ifp;
  	sc = sc_if->msk_softc;
 -	switch (sc->msk_hw_id) {
 -	case CHIP_ID_YUKON_EX:
 -		if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
 -			goto yukon_ex_workaround;
 -		if (ifp->if_mtu > ETHERMTU)
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_ENA);
 -		else
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 -		break;
 -	default:
 -yukon_ex_workaround:
 +	if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
 +	    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
 +	    sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
 +		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +		    TX_STFW_ENA);
 +	} else {
  		if (ifp->if_mtu > ETHERMTU) {
  			/* Set Tx GMAC FIFO Almost Empty Threshold. */
  			CSR_WRITE_4(sc,
  			    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
  			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
  			/* Disable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_ENA | TX_STFW_DIS);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_DIS);
  		} else {
 -			/* Enable Store & Forward mode for Tx. */
 -			CSR_WRITE_4(sc,
 -			    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 -			    TX_JUMBO_DIS | TX_STFW_ENA);
 +			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
 +			    TX_STFW_ENA);
  		}
 -		break;
  	}
  }
  
 
 Modified: stable/7/sys/dev/msk/if_mskreg.h
 ==============================================================================
 --- stable/7/sys/dev/msk/if_mskreg.h	Wed Jun 22 01:42:52 2011	(r223396)
 +++ stable/7/sys/dev/msk/if_mskreg.h	Wed Jun 22 01:44:09 2011	(r223397)
 @@ -677,6 +677,7 @@
  /* ASF Subsystem Registers (Yukon-2 only) */
  #define B28_Y2_SMB_CONFIG	0x0e40	/* 32 bit ASF SMBus Config Register */
  #define B28_Y2_SMB_CSD_REG	0x0e44	/* 32 bit ASF SMB Control/Status/Data */
 +#define B28_Y2_CPU_WDOG		0x0e48	/* 32 bit Watchdog Register */
  #define B28_Y2_ASF_IRQ_V_BASE	0x0e60	/* 32 bit ASF IRQ Vector Base */
  #define B28_Y2_ASF_STAT_CMD	0x0e68	/* 32 bit ASF Status and Command Reg */
  #define B28_Y2_ASF_HCU_CCSR	0x0e68	/* 32 bit ASF HCU CCSR (Yukon EX) */
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State-Changed-From-To: feedback->closed 
State-Changed-By: yongari 
State-Changed-When: Fri Jun 24 00:48:12 UTC 2011 
State-Changed-Why:  
Fix merged to both stable/8 and stable/7. If you encounter the 
issue again please open a new PR. 
Thanks for reporting! 

http://www.freebsd.org/cgi/query-pr.cgi?pr=114631 
>Unformatted:
