From nobody@FreeBSD.org  Wed May  4 13:21:47 2011
Return-Path: <nobody@FreeBSD.org>
Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34])
	by hub.freebsd.org (Postfix) with ESMTP id 199001065677
	for <freebsd-gnats-submit@FreeBSD.org>; Wed,  4 May 2011 13:21:47 +0000 (UTC)
	(envelope-from nobody@FreeBSD.org)
Received: from red.freebsd.org (red.freebsd.org [IPv6:2001:4f8:fff6::22])
	by mx1.freebsd.org (Postfix) with ESMTP id 07FE58FC1F
	for <freebsd-gnats-submit@FreeBSD.org>; Wed,  4 May 2011 13:21:47 +0000 (UTC)
Received: from red.freebsd.org (localhost [127.0.0.1])
	by red.freebsd.org (8.14.4/8.14.4) with ESMTP id p44DLkhp085850
	for <freebsd-gnats-submit@FreeBSD.org>; Wed, 4 May 2011 13:21:46 GMT
	(envelope-from nobody@red.freebsd.org)
Received: (from nobody@localhost)
	by red.freebsd.org (8.14.4/8.14.4/Submit) id p44DLk0e085841;
	Wed, 4 May 2011 13:21:46 GMT
	(envelope-from nobody)
Message-Id: <201105041321.p44DLk0e085841@red.freebsd.org>
Date: Wed, 4 May 2011 13:21:46 GMT
From: Arnaud <vancorte@biologie.ens.fr>
To: freebsd-gnats-submit@FreeBSD.org
Subject: OpenRD Ultimate does not boot on DB-88F6XXX or SHEEVAPLUG kernel configurations
X-Send-Pr-Version: www-3.1
X-GNATS-Notify:

>Number:         156814
>Category:       arm
>Synopsis:       OpenRD Ultimate does not boot on DB-88F6XXX or SHEEVAPLUG kernel configurations
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    hrs
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:  
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Wed May 04 13:30:10 UTC 2011
>Closed-Date:    
>Last-Modified:  Sat Oct 27 10:30:00 UTC 2012
>Originator:     Arnaud
>Release:        9.0-CURRENT
>Organization:
Ecole Normale Superieure
>Environment:
FreeBSD OpenRD-Ultimate 9.0-CURRENT FreeBSD 9.0-CURRENT #0: Tue May  3 14:31:36 UTC 2011     root@OpenRD-Ultimate:/usr/obj/usr/src/sys/OPENRD-FBSD9  arm

>Description:
Hi,

I was not able to boot my OpenRD Ultimate using DB-88F6XXX or SHEEVAPLUG kernels which are designed for device configurations close to mine.

Here is the solution I found, notably based on N.Shigemura work.

Two problems have been solved:

- boot by modifying the FDT
- use the two mge network interfaces

>How-To-Repeat:
Load one of these kernels, it should freeze the openrd box 

>Fix:
Referring to an almost 1 year old thread (http://markmail.org/message/4vjllpvhotkshg6n), I have been able to have a working configuration with those modifications :

- create an OPENRD kernel config based on DB-88F6XXX
- using the openrd.dts file (written by N.Shigemura) 
- applying the patch of N.shigemura on mge driver
- patching mgevar headers

I send you a diff of my modifications.

I am aware that some of these modifications could be a step back in developments that have been made during last months. I hope it will help developers.


Regards.

Patch attached with submission follows:

diff -Nur src/sys/arm/conf/OPENRD src/sys/arm/conf/OPENRD
--- src/sys/arm/conf/OPENRD	1970-01-01 00:00:00.000000000 +0000
+++ src/sys/arm/conf/OPENRD	2011-05-04 13:57:37.000000000 +0000
@@ -0,0 +1,90 @@
+#
+# Custom kernel for Marvell OpenRD devices.
+#
+# 
+#
+
+ident		OPENRD
+include		"../mv/kirkwood/std.db88f6xxx"
+
+options 	SOC_MV_KIRKWOOD
+makeoptions	MODULES_OVERRIDE=""
+
+#makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
+makeoptions	WERROR="-Werror"
+
+options 	SCHED_4BSD		#4BSD scheduler
+options 	INET			#InterNETworking
+options 	INET6			#IPv6 communications protocols
+options 	FFS			#Berkeley Fast Filesystem
+options 	NFSCLIENT		#Network Filesystem Client
+options 	NFSLOCKD		#Network Lock Manager
+options 	NFS_ROOT		#NFS usable as /, requires NFSCLIENT
+options 	BOOTP
+options 	BOOTP_NFSROOT
+options 	BOOTP_NFSV3
+options 	BOOTP_WIRED_TO=mge0
+
+#options 	ROOTDEVNAME=\"ufs:/dev/da0a\"
+
+options 	SYSVSHM			#SYSV-style shared memory
+options 	SYSVMSG			#SYSV-style message queues
+options 	SYSVSEM			#SYSV-style semaphores
+options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+options 	MUTEX_NOINLINE
+options 	RWLOCK_NOINLINE
+options 	NO_FFS_SNAPSHOT
+options 	NO_SWAPPING
+
+# Debugging
+options 	ALT_BREAK_TO_DEBUGGER
+options 	DDB
+#options	DEADLKRES               #Enable the deadlock resolver
+options 	DIAGNOSTIC
+#options	INVARIANTS              #Enable calls of extra sanity checking
+#options	INVARIANT_SUPPORT       #Extra sanity checks of internal structures, required by INVARIANTS
+options 	KDB
+options 	WITNESS                 #Enable checks to detect deadlocks and cycles
+options 	WITNESS_SKIPSPIN        #Don't run witness on spinlocks for speed
+#options	WITNESS_KDB
+
+device		pci
+
+# Pseudo devices
+device		loop
+device		md
+device		pty
+device		random
+
+# Serial ports
+device		uart
+
+# Networking
+device		ether
+device		mge			# Marvell Gigabit Ethernet controller
+device		mii
+device		e1000phy
+device		bpf
+
+# USB
+options 	USB_DEBUG	# enable debug msgs
+device		usb
+device		ehci
+device		umass
+device		scbus
+device		pass
+device		da
+
+# I2C (TWSI)
+device		iic
+device		iicbus
+
+# SATA
+device		mvs
+device		ata
+device		atadisk
+
+# Flattened Device Tree
+options 	FDT
+options 	FDT_DTB_STATIC
+makeoptions	FDT_DTS_FILE=openrd.dts
diff -Nur src/sys/boot/fdt/dts/openrd.dts src/sys/boot/fdt/dts/openrd.dts
--- src/sys/boot/fdt/dts/openrd.dts	1970-01-01 00:00:00.000000000 +0000
+++ src/sys/boot/fdt/dts/openrd.dts	2011-05-04 13:52:17.000000000 +0000
@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2009-2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * OpenRD-Client/Ultimate Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+	model = "mrvl,OpenRD-CL";
+	compatible = "OpenRD-CL";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		ethernet0 = &enet0;
+		ethernet1 = &enet1;
+		mpp = &MPP;
+		pci0 = &pci0;
+		serial0 = &serial0;
+		serial1 = &serial1;
+		soc = &SOC;
+		sram = &SRAM;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "ARM,88FR131";
+			reg = <0x0>;
+			d-cache-line-size = <32>;	// 32 bytes
+			i-cache-line-size = <32>;	// 32 bytes
+			d-cache-size = <0x4000>;	// L1, 16K
+			i-cache-size = <0x4000>;	// L1, 16K
+			timebase-frequency = <0>;
+			bus-frequency = <0>;
+			clock-frequency = <0>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;		// 512M@0x0
+	};
+
+	localbus@f1000000 {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		compatible = "mrvl,lbc";
+
+		/* This reflects CPU decode windows setup. */
+		ranges = <0x0 0x0f 0xf9300000 0x00100000
+			  0x1 0x1e 0xfa000000 0x00100000
+			  0x2 0x1d 0xfa100000 0x02000000
+			  0x3 0x1b 0xfc100000 0x00000400>;
+
+		nor@0,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x0 0x0 0x00100000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		led@1,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "led";
+			reg = <0x1 0x0 0x00100000>;
+		};
+
+		nor@2,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x2 0x0 0x02000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand@3,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x3 0x0 0x00100000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+	};
+
+	SOC: soc88f6281@f1000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges = <0x0 0xf1000000 0x00100000>;
+		bus-frequency = <0>;
+
+		PIC: pic@20200 {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			reg = <0x20200 0x3c>;
+			compatible = "mrvl,pic";
+		};
+
+		timer@20300 {
+			compatible = "mrvl,timer";
+			reg = <0x20300 0x30>;
+			interrupts = <1>;
+			interrupt-parent = <&PIC>;
+			mrvl,has-wdt;
+		};
+
+		MPP: mpp@10000 {
+			#pin-cells = <2>;
+			compatible = "mrvl,mpp";
+			reg = <0x10000 0x34>;
+			pin-count = <50>;
+			pin-map = <
+				0  1		/* MPP[0]:  NF_IO[2] */
+				1  1		/* MPP[1]:  NF_IO[3] */
+				2  1		/* MPP[2]:  NF_IO[4] */
+				3  1		/* MPP[3]:  NF_IO[5] */
+				4  1		/* MPP[4]:  NF_IO[6] */
+				5  1		/* MPP[5]:  NF_IO[7] */
+				6  1		/* MPP[6]:  SYSRST_OUTn */
+				7  0		/* MPP[7]:  GPO[7] */
+				8  1		/* MPP[8]:  TW_SDA */
+				9  1		/* MPP[9]:  TW_SCK */
+				10 3		/* MPP[10]: UA0_TXD */
+				11 3		/* MPP[11]: UA0_RXD */
+				12 1		/* MPP[12]: SD_CLK */
+				13 1		/* MPP[13]: SD_CMD */
+				14 1		/* MPP[14]: SD_D[0] */
+				15 1		/* MPP[15]: SD_D[1] */
+				16 1		/* MPP[16]: SD_D[2] */
+				17 1		/* MPP[17]: SD_D[3] */
+				18 1		/* MPP[18]: NF_IO[0] */
+				19 1		/* MPP[19]: NF_IO[1] */
+				20 3		/* MPP[20]: GE1[0] */
+				21 3		/* MPP[21]: GE1[1] */
+				22 3		/* MPP[22]: GE1[2] */
+				23 3		/* MPP[23]: GE1[3] */
+				24 3		/* MPP[24]: GE1[4] */
+				25 3		/* MPP[25]: GE1[5] */
+				26 3		/* MPP[26]: GE1[6] */
+				27 3		/* MPP[27]: GE1[7] */
+				28 0		/* MPP[28]: GPIO[28] */
+				29 1		/* MPP[29]: TSMP[9] */
+				30 3		/* MPP[30]: GE1[10] */
+				31 3		/* MPP[31]: GE1[11] */
+				32 3		/* MPP[32]: GE1[12] */
+				33 3		/* MPP[33]: GE1[13] */
+				34 0		/* MPP[34]: GPIO[34] */
+				35 2		/* MPP[35]: TDM_CH0_TX_QL */
+				36 2		/* MPP[36]: TDM_SPI_CS1 */
+				37 2		/* MPP[37]: TDM_CH2_TX_QL */
+				38 2		/* MPP[38]: TDM_CH2_RX_QL */
+				39 4		/* MPP[39]: AU_I2SBCLK */
+				40 4		/* MPP[40]: AU_I2SDO */
+				41 4		/* MPP[41]: AU_I2SLRCLK */
+				42 4		/* MPP[42]: AU_I2SMCLK */
+				43 4		/* MPP[43]: AU_I2SDI */
+				44 4		/* MPP[44]: AU_EXTCLK */
+				45 2		/* MPP[45]: TDM_PCLK */
+				46 2		/* MPP[46]: TDM_FS */
+				47 2		/* MPP[47]: TDM_DRX */
+				48 2		/* MPP[48]: TDM_DTX */
+				49 2>;		/* MPP[49]: TDM_CH0_TX_QL */
+		};
+
+		GPIO: gpio@10100 {
+			#gpio-cells = <3>;
+			compatible = "mrvl,gpio";
+			reg = <0x10100 0x20>;
+			gpio-controller;
+			interrupts = <35 36 37 38 39 40 41>;
+			interrupt-parent = <&PIC>;
+		};
+
+		rtc@10300 {
+			compatible = "mrvl,rtc";
+			reg = <0x10300 0x08>;
+		};
+
+		twsi@11000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "mrvl,twsi";
+			reg = <0x11000 0x20>;
+			interrupts = <43>;
+			interrupt-parent = <&PIC>;
+		};
+
+		enet0: ethernet@72000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			model = "V2";
+			compatible = "mrvl,ge";
+			reg = <0x72000 0x2000>;
+			ranges = <0x0 0x72000 0x2000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <12 13 14 11 46>;
+			interrupt-parent = <&PIC>;
+
+			mdio@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "mrvl,mdio";
+			};
+		};
+
+		enet1: ethernet@76000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			model = "V2";
+			compatible = "mrvl,ge";
+			reg = <0x76000 0x2000>;
+			ranges = <0x0 0x76000 0x2000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <16 17 18 15 47>;
+			interrupt-parent = <&PIC>;
+
+			mdio@1 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "mrvl,mdio";
+			};
+		};
+
+		serial0: serial@12000 {
+			compatible = "ns16550";
+			reg = <0x12000 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <0>;
+			interrupts = <33>;
+			interrupt-parent = <&PIC>;
+		};
+
+		serial1: serial@12100 {
+			compatible = "ns16550";
+			reg = <0x12100 0x20>;
+			reg-shift = <2>;
+			clock-frequency = <0>;
+			interrupts = <34>;
+			interrupt-parent = <&PIC>;
+		};
+
+		crypto@30000 {
+			compatible = "mrvl,cesa";
+			reg = <0x30000 0x10000>;
+			interrupts = <22>;
+			interrupt-parent = <&PIC>;
+		};
+
+		usb@50000 {
+			compatible = "mrvl,usb-ehci", "usb-ehci";
+			reg = <0x50000 0x1000>;
+			interrupts = <48 19>;
+			interrupt-parent = <&PIC>;
+		};
+
+		xor@60000 {
+			compatible = "mrvl,xor";
+			reg = <0x60000 0x1000>;
+			interrupts = <5 6 7 8>;
+			interrupt-parent = <&PIC>;
+		};
+
+		sata@80000 {
+			compatible = "mrvl,sata";
+			reg = <0x80000 0x6000>;
+			interrupts = <21>;
+			interrupt-parent = <&PIC>;
+		};
+	};
+
+	SRAM: sram@fd000000 {
+		compatible = "mrvl,cesa-sram";
+		reg = <0xfd000000 0x00100000>;
+	};
+
+	chosen {
+		stdin  = "serial0";
+		stdout = "serial0";
+	};
+
+	pci0: pcie@f1040000 {
+		compatible = "mrvl,pcie";
+		device_type = "pci";
+		#interrupt-cells = <1>;
+		#size-cells = <2>;
+		#address-cells = <3>;
+		reg = <0xf1040000 0x2000>;
+		bus-range = <0 255>;
+		ranges = <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x04000000
+			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
+		clock-frequency = <33333333>;
+		interrupt-parent = <&PIC>;
+		interrupts = <44>;
+		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+		interrupt-map = <
+			/* IDSEL 0x1 */
+			0x0800 0x0 0x0 0x1 &PIC 0x9
+			0x0800 0x0 0x0 0x2 &PIC 0x9
+			0x0800 0x0 0x0 0x3 &PIC 0x9
+			0x0800 0x0 0x0 0x4 &PIC 0x9
+			>;
+		pcie@0 {
+			reg = <0x0 0x0 0x0 0x0 0x0>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			device_type = "pci";
+			ranges = <0x02000000 0x0 0xf4000000
+				  0x02000000 0x0 0xf4000000
+				  0x0 0x04040000
+
+				  0x01000000 0x0 0x0
+				  0x01000000 0x0 0x0
+				  0x0 0x00100000>;
+		};
+	};
+};
+
diff -Nur src/sys/dev/mge/if_mge.c src/sys/dev/mge/if_mge.c
--- src/sys/dev/mge/if_mge.c	2011-05-04 13:45:36.000000000 +0000
+++ src/sys/dev/mge/if_mge.c	2011-05-04 13:52:59.000000000 +0000
@@ -626,10 +626,9 @@
 mge_attach(device_t dev)
 {
 	struct mge_softc *sc;
-	struct mii_softc *miisc;
 	struct ifnet *ifp;
 	uint8_t hwaddr[ETHER_ADDR_LEN];
-	int i, error, phy;
+	int i, error;
 
 	sc = device_get_softc(dev);
 	sc->dev = dev;
@@ -642,8 +641,8 @@
 	mge_ver_params(sc);
 
 	/* Get phy address from fdt */
-	if (fdt_get_phyaddr(sc->node, &phy) != 0)
-		return (ENXIO);
+	if (fdt_get_phyaddr(sc->node, &sc->phyaddr) != 0)
+		sc->phyaddr = -1;
 
 	/* Initialize mutexes */
 	mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
@@ -674,6 +673,9 @@
 	sc->tx_ic_time = 768;
 	mge_add_sysctls(sc);
 
+	if (sc->phyaddr == -1)
+		sc->phyaddr = MGE_READ(sc, MGE_REG_PHYDEV);
+
 	/* Allocate network interface */
 	ifp = sc->ifp = if_alloc(IFT_ETHER);
 	if (ifp == NULL) {
@@ -708,7 +710,7 @@
 
 	/* Attach PHY(s) */
 	error = mii_attach(dev, &sc->miibus, ifp, mge_ifmedia_upd,
-	    mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
+	    mge_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 0);
 	if (error) {
 		device_printf(dev, "attaching PHYs failed\n");
 		mge_detach(dev);
@@ -717,8 +719,7 @@
 	sc->mii = device_get_softc(sc->miibus);
 
 	/* Tell the MAC where to find the PHY so autoneg works */
-	miisc = LIST_FIRST(&sc->mii->mii_phys);
-	MGE_WRITE(sc, MGE_REG_PHYDEV, miisc->mii_phy);
+	MGE_WRITE(sc, MGE_REG_PHYDEV, sc->phyaddr); 
 
 	/* Attach interrupt handlers */
 	for (i = 0; i < 2; ++i) {
@@ -868,8 +869,7 @@
 	struct mge_softc *sc = arg;
 	struct mge_desc_wrapper *dw;
 	volatile uint32_t reg_val;
-	int i, count;
-
+	int i;
 
 	MGE_GLOBAL_LOCK_ASSERT(sc);
 
@@ -949,17 +949,6 @@
 	reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
 	reg_val |= PORT_SERIAL_ENABLE;
 	MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
-	count = 0x100000;
-	for (;;) {
-		reg_val = MGE_READ(sc, MGE_PORT_STATUS);
-		if (reg_val & MGE_STATUS_LINKUP)
-			break;
-		DELAY(100);
-		if (--count == 0) {
-			if_printf(sc->ifp, "Timeout on link-up\n");
-			break;
-		}
-	}
 
 	/* Setup interrupts coalescing */
 	mge_set_rxic(sc);
@@ -1484,8 +1473,8 @@
 
 	MGE_TRANSMIT_LOCK_ASSERT(sc);
 
-	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
-	    IFF_DRV_RUNNING)
+	if (IFM_SUBTYPE(sc->mii->mii_media_active) == IFM_NONE ||
+	    (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
 		return;
 
 	for (;;) {
diff -Nur src/sys/dev/mge/if_mgevar.h src/sys/dev/mge/if_mgevar.h
--- src/sys/dev/mge/if_mgevar.h	2011-05-04 13:45:36.000000000 +0000
+++ src/sys/dev/mge/if_mgevar.h	2011-05-04 13:52:59.000000000 +0000
@@ -103,6 +103,7 @@
 	uint32_t	mge_tx_tok_cnt;
 	uint16_t	mge_mtu;
 	int		mge_ver;
+	int		phyaddr;
 };
 
 


>Release-Note:
>Audit-Trail:

From: Freddy DISSAUX <freddy.dsx@free.fr>
To: bug-followup@FreeBSD.org, vancorte@biologie.ens.fr
Cc:  
Subject: Re: arm/156814: OpenRD Ultimate does not boot on DB-88F6XXX or
	SHEEVAPLUG kernel configurations
Date: Tue, 17 May 2011 19:40:08 +0200

 Hello,
 
 My dmesg:
 
 KDB: debugger backends: ddb
 KDB: current backend: ddb
 Copyright (c) 1992-2011 The FreeBSD Project.
 Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
 	The Regents of the University of California. All rights reserved.
 FreeBSD is a registered trademark of The FreeBSD Foundation.
 FreeBSD 9.0-CURRENT #0: Thu May  5 08:17:13 UTC 2011
     root@openrd.bsdsx.fr:/usr/obj/usr/src/sys/OPENRD arm
 WARNING: WITNESS option enabled, expect reduced performance.
 WARNING: DIAGNOSTIC option enabled, expect reduced performance.
 module mvs already present!
 CPU: Feroceon 88FR131 rev 1 (Marvell core)
   DC enabled IC enabled WB enabled EABT branch prediction enabled
   16KB/32B 4-way Instruction cache
   16KB/32B 4-way write-back-locking-C Data cache
 real memory  = 536870912 (512 MB)
 avail memory = 518627328 (494 MB)
 SOC: Marvell 88F6281 rev A0, TClock 200MHz
 simplebus0: <Flattened device tree simple bus> on fdtbus0
 ic0: <Marvell Integrated Interrupt Controller> mem 0xf1020200-0xf102023b on simplebus0
 timer0: <Marvell CPU Timer> mem 0xf1020300-0xf102032f irq 1 on simplebus0
 Event timer "CPUTimer0" frequency 200000000 Hz quality 1000
 Timecounter "CPUTimer1" frequency 200000000 Hz quality 1000
 gpio0: <Marvell Integrated GPIO Controller> mem 0xf1010100-0xf101011f irq 35,36,37,38,39,40,41 on simplebus0
 rtc0: <Marvell Integrated RTC> mem 0xf1010300-0xf1010307 on simplebus0
 twsi0: <Marvell Integrated I2C Bus Controller> mem 0xf1011000-0xf101101f irq 43 on simplebus0
 iicbus0: <Philips I2C bus> on twsi0
 iic0: <I2C generic I/O> on iicbus0
 mge0: <Marvell Gigabit Ethernet controller> mem 0xf1072000-0xf1073fff irq 12,13,14,11,46 on simplebus0
 mge0: Ethernet address: 00:50:43:01:db:4d
 miibus0: <MII bus> on mge0
 e1000phy0: <Marvell 88E1116R Gigabit PHY> PHY 8 on miibus0
 e1000phy0:  none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-master, 1000baseT-FDX, 1000baseT-FDX-master, auto
 mge1: <Marvell Gigabit Ethernet controller> mem 0xf1076000-0xf1077fff irq 16,17,18,15,47 on simplebus0
 mge1: Ethernet address: 00:50:43:01:db:4e
 miibus1: <MII bus> on mge1
 e1000phy1: <Marvell 88E1116R Gigabit PHY> PHY 24 on miibus1
 e1000phy1:  none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-master, 1000baseT-FDX, 1000baseT-FDX-master, auto
 uart0: <16550 or compatible> mem 0xf1012000-0xf101201f irq 33 on simplebus0
 uart0: console (1066,n,8,1)
 uart1: <16550 or compatible> mem 0xf1012100-0xf101211f irq 34 on simplebus0
 ehci0: <Marvell Integrated USB 2.0 controller> mem 0xf1050000-0xf1050fff irq 48,19 on simplebus0
 usbus0: EHCI version 1.0
 usbus0: set host controller mode
 usbus0: <Marvell Integrated USB 2.0 controller> on ehci0
 sata0: <Marvell Integrated SATA Controller> mem 0xf1080000-0xf1085fff irq 21 on simplebus0
 ata0: <Marvell Integrated SATA Channel> on sata0
 ata1: <Marvell Integrated SATA Channel> on sata0
 pcib0: <Marvell Integrated PCI/PCI-E Controller> mem 0xf1040000-0xf1041fff irq 44 on fdtbus0
 pcib0: PCI IO/Memory space exhausted
 device_attach: pcib0 attach returned 12
 Timecounters tick every 10.000 msec
 usbus0: 480Mbps High Speed USB v2.0
 ad0: 238475MB <SAMSUNG HM250HI 2AC101C4> at ata0-master UDMA100 SATA 3Gb/s
 WARNING: WITNESS option enabled, expect reduced performance.
 WARNING: DIAGNOSTIC option enabled, expect reduced performance.
 ugen0.1: <Marvell> at usbus0
 uhub0: <Marvell EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on usbus0
 uhub0: 1 port with 1 removable, self powered
 Root mount waiting for: usbus0
 ugen0.2: <vendor 0x0424> at usbus0
 uhub1: <vendor 0x0424 product 0x2517, class 9/0, rev 2.00/0.01, addr 2> on usbus0
 Root mount waiting for: usbus0
 uhub1: 7 ports with 7 removable, self powered
 ugen0.3: <Kingston> at usbus0
 umass0: <Kingston DataTraveler 2.00000000184, class 0/0, rev 2.00/2.00, addr 3> on usbus0
 umass0:  SCSI over Bulk-Only; quirks = 0x0000
 Root mount waiting for: usbus0
 Root mount waiting for: usbus0
 umass0:0:0:-1: Attached to scbus0
 Trying to mount root from ufs:/dev/ad0s1g []...
 da0 at umass-sim0 bus 0 scbus0 target 0 lun 0
 da0: <Kingston DataTraveler 2.0 1.00> Removable Direct Access SCSI-2 device 
 da0: 40.000MB/s transfers
 da0: 953MB (1952256 512 byte sectors: 64H 32S/T 953C)
 GEOM: da0: geometry does not match label (255h,63s != 64h,32s).
 lock order reversal:
  1st 0xc35b10b0 pmap (pmap) @ /usr/src/sys/arm/arm/pmap.c:922
  2nd 0xc0d76dc0 vm page queue mutex (vm page queue mutex) @ /usr/src/sys/arm/arm/pmap.c:1618
 KDB: stack backtrace:
 db_md_set_watchpoint() at db_md_set_watchpoint+0x18
 scp=0xc0b2d4ec rlv=0xc0924d20 (X_db_sym_numargs+0x178)
 	rsp=0xcf7917dc rfp=0xcf7918f8
 	r10=0xc356a318 r9=0x00000652
 	r8=0xc0d46184 r7=0xc356a110 r6=0xffffffff r5=0xc0b5994c
 	r4=0xcf7917e4
 X_db_sym_numargs() at X_db_sym_numargs+0x154
 scp=0xc0924cfc rlv=0xc0a186f8 (kdb_backtrace+0x3c)
 	rsp=0xcf7918fc rfp=0xcf79190c
 	r4=0xc0c16ec0
 kdb_backtrace() at kdb_backtrace+0x10
 scp=0xc0a186cc rlv=0xc0a2945c (witness_display_spinlock+0xac)
 	rsp=0xcf791910 rfp=0xcf791924
 	r4=0x00000001
 witness_display_spinlock() at witness_display_spinlock+0x64
 scp=0xc0a29414 rlv=0xc0a29f84 (witness_checkorder+0x5f4)
 	rsp=0xcf791928 rfp=0xcf791970
 	r5=0xc0d76dc0 r4=0x00000000
 witness_checkorder() at witness_checkorder+0x10
 scp=0xc0a299a0 rlv=0xc09e18a4 (_mtx_lock_flags+0x34)
 	rsp=0xcf791974 rfp=0xcf79199c
 	r10=0xc0d82680 r9=0x00008000
 	r8=0x00000652 r7=0xc0b95f68 r6=0x00000000 r5=0x00000000
 	r4=0xc0d76dc0
 _mtx_lock_flags() at _mtx_lock_flags+0x10
 scp=0xc09e1880 rlv=0xc0b32db4 (pmap_extract+0x2c0)
 	rsp=0xcf7919a0 rfp=0xcf7919c8
 	r10=0x00000012 r8=0x00000000
 	r7=0xc0f3aa6c r6=0xc35b10b0 r5=0xc0f3aa3c r4=0xc183d01c
 pmap_extract() at pmap_extract+0x1ac
 scp=0xc0b32ca0 rlv=0xc0b37674 (pmap_release+0xdc8)
 	rsp=0xcf7919cc rfp=0xcf791a48
 	r10=0x00000000 r9=0x00000000
 	r8=0xc38a6800 r7=0xc35b10b0 r6=0x00000000 r5=0xc38a4e90
 	r4=0x01f1500e
 pmap_release() at pmap_release+0x298
 scp=0xc0b36b44 rlv=0xc0b37c48 (pmap_enter_object+0xa0)
 	rsp=0xcf791a4c rfp=0xcf791a80
 	r10=0xc35b10b0 r9=0x00000005
 	r8=0xc0f3aa3c r7=0x00000000 r6=0x0000006b r5=0xc0f3aa3c
 	r4=0x00000001
 pmap_enter_object() at pmap_enter_object+0x10
 scp=0xc0b37bb8 rlv=0xc0b1581c (vm_map_pmap_enter+0x220)
 	rsp=0xcf791a84 rfp=0xcf791ad0
 	r10=0x00000000 r9=0x00000000
 	r8=0x00000000 r7=0x0000006b r6=0x00000000 r5=0x00000000
 	r4=0x0000000f
 vm_map_pmap_enter() at vm_map_pmap_enter+0x14
 scp=0xc0b15610 rlv=0xc0b15e50 (vm_map_insert+0x298)
 	rsp=0xcf791ad4 rfp=0xcf791b20
 	r10=0xc0e90b28 r9=0xc35b1000
 	r8=0x00000000 r7=0x00000000 r6=0x00000000 r5=0x00000000
 	r4=0x00000000
 vm_map_insert() at vm_map_insert+0x10
 scp=0xc0b15bc8 rlv=0xc09b07d4 (elf32_remove_brand_entry+0x510)
 	rsp=0xcf791b24 rfp=0xcf791b68
 	r10=0x00073000 r9=0x00008000
 	r8=0xc35b1000 r7=0x00000000 r6=0x00000000 r5=0x00000005
 	r4=0x00000000
 elf32_remove_brand_entry() at elf32_remove_brand_entry+0x2c8
 scp=0xc09b058c rlv=0xc09b08e8 (elf32_remove_brand_entry+0x624)
 	rsp=0xcf791b6c rfp=0xcf791bac
 	r10=0x0006ae00 r9=0x00008000
 	r8=0xc0e90b28 r7=0x00000000 r6=0x0006ae00 r5=0xfffff000
 	r4=0x00073000
 elf32_remove_brand_entry() at elf32_remove_brand_entry+0x554
 scp=0xc09b0818 rlv=0xc09b1f28 (elf32_brand_inuse+0x61c)
 	rsp=0xcf791bb0 rfp=0xcf791c4c
 	r10=0xcf795034 r9=0x00000000
 	r8=0xc0bff9a8 r7=0xcf795000 r6=0xcf791cec r5=0x00000000
 	r4=0x00008000
 elf32_brand_inuse() at elf32_brand_inuse+0xb4
 scp=0xc09b19c0 rlv=0xc09c83d8 (kern_execve+0x278)
 	rsp=0xcf791c50 rfp=0xcf791de4
 	r10=0x00000000 r9=0xc35af000
 	r8=0xcf791cec r7=0x00000000 r6=0xc0c08070 r5=0x00000000
 	r4=0x00000001
 kern_execve() at kern_execve+0x10
 scp=0xc09c8170 rlv=0xc09c8fac (execve+0x48)
 	rsp=0xcf791de8 rfp=0xcf791e28
 	r10=0xbffffffd r9=0xc35ac000
 	r8=0xc0be7070 r7=0xc0be707a r6=0xbffffff2 r5=0xcf791dec
 	r4=0xc35af000
 execve() at execve+0x10
 scp=0xc09c8f74 rlv=0xc09b2dac (exec_shell_imgact+0x914)
 	rsp=0xcf791e2c rfp=0xcf791e80
 	r5=0xbfffffe4 r4=0xbfffffe8
 exec_shell_imgact() at exec_shell_imgact+0x738
 scp=0xc09b2bd0 rlv=0xc09cb3b8 (fork_exit+0x64)
 	rsp=0xcf791e84 rfp=0xcf791ea8
 	r10=0xc09b2bc0 r9=0x00000000
 	r8=0x00000000 r7=0xcf791eac r6=0xc35ac000 r5=0xc0d82680
 	r4=0xc35af000
 fork_exit() at fork_exit+0x10
 scp=0xc09cb364 rlv=0xc0b3c25c (fork_trampoline+0x14)
 	rsp=0xcf791eac rfp=0x00000000
 	r10=0x00000000 r8=0x00000000
 	r7=0x00000000 r6=0x00000000 r5=0x00000000 r4=0xc09b2bc0
 lock order reversal:
  1st 0xc35b0a78 pmap (pmap) @ /usr/src/sys/arm/arm/pmap.c:922
  2nd 0xc0d815a4 vm object (uma object) @ /usr/src/sys/vm/uma_core.c:1026
 KDB: stack backtrace:
 db_md_set_watchpoint() at db_md_set_watchpoint+0x18
 scp=0xc0b2d4ec rlv=0xc0924d20 (X_db_sym_numargs+0x178)
 	rsp=0xd2001964 rfp=0xd2001a80
 	r10=0xc356a318 r9=0x00000402
 	r8=0xc0d46184 r7=0xc356aa68 r6=0xffffffff r5=0xc0b5994c
 	r4=0xd200196c
 X_db_sym_numargs() at X_db_sym_numargs+0x154
 scp=0xc0924cfc rlv=0xc0a186f8 (kdb_backtrace+0x3c)
 	rsp=0xd2001a84 rfp=0xd2001a94
 	r4=0xc0c16ec0
 kdb_backtrace() at kdb_backtrace+0x10
 scp=0xc0a186cc rlv=0xc0a2945c (witness_display_spinlock+0xac)
 	rsp=0xd2001a98 rfp=0xd2001aac
 	r4=0x00000001
 witness_display_spinlock() at witness_display_spinlock+0x64
 scp=0xc0a29414 rlv=0xc0a29f84 (witness_checkorder+0x5f4)
 	rsp=0xd2001ab0 rfp=0xd2001af8
 	r5=0xc0d815a4 r4=0x00000000
 witness_checkorder() at witness_checkorder+0x10
 scp=0xc0a299a0 rlv=0xc09e18a4 (_mtx_lock_flags+0x34)
 	rsp=0xd2001afc rfp=0xd2001b24
 	r10=0xc0d82680 r9=0xc0ea06e0
 	r8=0x00000402 r7=0xc0b92c14 r6=0x00000000 r5=0x00000000
 	r4=0xc0d815a4
 _mtx_lock_flags() at _mtx_lock_flags+0x10
 scp=0xc09e1880 rlv=0xc0b0be24 (uma_print_zone+0x2a0)
 	rsp=0xd2001b28 rfp=0xd2001b64
 	r10=0x00001000 r8=0x00000101
 	r7=0x00000000 r6=0xc0ea06e0 r5=0xc0ea1600 r4=0xc0ea1600
 uma_print_zone() at uma_print_zone+0x274
 scp=0xc0b0bdf8 rlv=0xc0b0d7ec (uma_zcreate+0xd0)
 	rsp=0xd2001b68 rfp=0xd2001ba4
 	r10=0xc0b0bde8 r9=0xc0ea06e0
 	r8=0x00000101 r7=0x00000000 r6=0xc0ea06e0 r5=0x00000001
 	r4=0xc0ea1600
 uma_zcreate() at uma_zcreate+0x70
 scp=0xc0b0d78c rlv=0xc0b0dd64 (uma_prealloc+0x198)
 	rsp=0xd2001ba8 rfp=0xd2001bc8
 	r10=0xc0e97c48 r9=0x00000080
 	r8=0xc0ea06e0 r7=0x00000000 r6=0xc0ea06e0 r5=0x00000201
 	r4=0xc0ea1600
 uma_prealloc() at uma_prealloc+0xd4
 scp=0xc0b0dca0 rlv=0xc0b0de14 (uma_prealloc+0x248)
 	rsp=0xd2001bcc rfp=0xd2001be4
 	r7=0x00000069 r6=0xc0ea06e0
 	r5=0x00000001 r4=0xc0ea1600
 uma_prealloc() at uma_prealloc+0x21c
 scp=0xc0b0dde8 rlv=0xc0b0f094 (uma_zalloc_arg+0x32c)
 	rsp=0xd2001be8 rfp=0xd2001c2c
 	r6=0xc183dde8 r5=0x00000069
 	r4=0x00000069
 uma_zalloc_arg() at uma_zalloc_arg+0x10
 scp=0xc0b0ed78 rlv=0xc0b37578 (pmap_release+0xccc)
 	rsp=0xd2001c30 rfp=0xd2001cac
 	r10=0x00000000 r9=0x00000000
 	r8=0xc38a7000 r7=0xc35b0a78 r6=0x00000000 r5=0xc38a4c44
 	r4=0x01f3b00e
 pmap_release() at pmap_release+0x298
 scp=0xc0b36b44 rlv=0xc0b37d3c (pmap_enter+0x70)
 	rsp=0xd2001cb0 rfp=0xd2001ce0
 	r10=0x00000005 r9=0xc0d76dc0
 	r8=0xc0f3b584 r7=0x00023000 r6=0x00000000 r5=0xc35b0a78
 	r4=0xc0b95f68
 pmap_enter() at pmap_enter+0x10
 scp=0xc0b37cdc rlv=0xc0b12070 (vm_fault_hold+0x159c)
 	rsp=0xd2001ce4 rfp=0xd2001e0c
 	r10=0xd2001eac r9=0xc3854870
 	r8=0xc0e90b28 r7=0xc0f3b584 r6=0x00023000 r5=0xc35b09c8
 	r4=0x00000000
 vm_fault_hold() at vm_fault_hold+0x10
 scp=0xc0b10ae4 rlv=0xc0b1274c (vm_fault+0x20)
 	rsp=0xd2001e10 rfp=0xd2001e20
 	r10=0xd2001eac r9=0xc3854870
 	r8=0xc3853000 r7=0x00000000 r6=0x00023000 r5=0xc35b09c8
 	r4=0xc38548f8
 vm_fault() at vm_fault+0x10
 scp=0xc0b1273c rlv=0xc0b3c788 (prefetch_abort_handler+0x140)
 	rsp=0xd2001e24 rfp=0xd2001ea8
 prefetch_abort_handler() at prefetch_abort_handler+0x10
 scp=0xc0b3c658 rlv=0xc0b2ef78 (address_exception_entry+0x50)
 	rsp=0xd2001eac rfp=0xbfffe86c
 	r10=0x00000019 r9=0x00000012
 	r8=0x0006ad28 r7=0x0006a848 r6=0x00000001 r5=0xffff1004
 	r4=0x0007ae28
 mge0: link state changed to UP

From: Kristof Provost <kristof@sigsegv.be>
To: bug-followup@FreeBSD.org, vancorte@biologie.ens.fr
Cc:  
Subject: Re: arm/156814: OpenRD Ultimate does not boot on DB-%38%38F%36XXX or
 SHEEVAPLUG kernel configurations
Date: Mon, 9 Apr 2012 12:41:03 +0200

 --G4iJoqBmSsgzjUCe
 Content-Type: text/plain; charset=utf-8
 Content-Disposition: inline
 
 Hi,
 
 I've updated the config and device tree. 
 With the attached patch both MGE interfaces work, as does the crypto 
 accelerator.
 
 (Against current r234000)
 
 Regards,
 Kristof
 
 
 --G4iJoqBmSsgzjUCe
 Content-Type: text/x-diff; charset=utf-8
 Content-Disposition: attachment; filename="openrd-cl.patch"
 
 diff --git a/sys/arm/conf/OPENRD-CL b/sys/arm/conf/OPENRD-CL
 new file mode 100644
 index 0000000..25707ed
 --- /dev/null
 +++ b/sys/arm/conf/OPENRD-CL
 @@ -0,0 +1,81 @@
 +#
 +# Custom kernel for OpenRD Client/Ultimate devices.
 +#
 +# $FreeBSD$
 +#
 +
 +ident		OPENRD-CL
 +include		"../mv/kirkwood/std.sheevaplug"
 +
 +options 	SOC_MV_KIRKWOOD
 +makeoptions	MODULES_OVERRIDE=""
 +
 +makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
 +makeoptions	WERROR="-Werror"
 +makeoptions     INVARIANTS
 +
 +options 	SCHED_4BSD		#4BSD scheduler
 +options 	INET			#InterNETworking
 +options 	INET6			#IPv6 communications protocols
 +options 	FFS			#Berkeley Fast Filesystem
 +options 	NFSCL			#New Network Filesystem Client
 +options 	NFSLOCKD		#Network Lock Manager
 +options 	NFS_ROOT		#NFS usable as /, requires NFSCL
 +options 	BOOTP
 +options 	BOOTP_NFSROOT
 +options 	BOOTP_NFSV3
 +options 	BOOTP_WIRED_TO=mge0
 +
 +# Root fs on USB device
 +#options 	ROOTDEVNAME=\"ufs:/dev/da0a\"
 +
 +options 	SYSVSHM			#SYSV-style shared memory
 +options 	SYSVMSG			#SYSV-style message queues
 +options 	SYSVSEM			#SYSV-style semaphores
 +options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
 +options 	MUTEX_NOINLINE
 +options 	RWLOCK_NOINLINE
 +options 	NO_FFS_SNAPSHOT
 +options 	NO_SWAPPING
 +
 +# Debugging
 +options 	ALT_BREAK_TO_DEBUGGER
 +options 	DDB
 +options 	KDB
 +
 +# Pseudo devices
 +device		random
 +device		pty
 +device		loop
 +
 +# Serial ports
 +device		uart
 +
 +# Networking
 +device		ether
 +device		mge			# Marvell Gigabit Ethernet controller
 +device		mii
 +device		e1000phy
 +device		bpf
 +options		HZ=1000
 +options		DEVICE_POLLING
 +device		vlan
 +
 +device		cesa			# Marvell security engine
 +device		crypto
 +device		cryptodev
 +
 +# USB
 +options 	USB_DEBUG	# enable debug msgs
 +device		usb
 +device		ehci
 +device		umass
 +device		scbus
 +device		pass
 +device		da
 +
 +# Flattened Device Tree
 +options 	FDT
 +options		FDT_DTB_STATIC
 +makeoptions	FDT_DTS_FILE=openrd-cl.dts
 +
 diff --git a/sys/boot/fdt/dts/openrd-cl.dts b/sys/boot/fdt/dts/openrd-cl.dts
 new file mode 100644
 index 0000000..6d11779
 --- /dev/null
 +++ b/sys/boot/fdt/dts/openrd-cl.dts
 @@ -0,0 +1,340 @@
 +/*
 + * Copyright (c) 2009-2010 The FreeBSD Foundation
 + * All rights reserved.
 + *
 + * This software was developed by Semihalf under sponsorship from
 + * the FreeBSD Foundation.
 + *
 + * Redistribution and use in source and binary forms, with or without
 + * modification, are permitted provided that the following conditions
 + * are met:
 + * 1. Redistributions of source code must retain the above copyright
 + *    notice, this list of conditions and the following disclaimer.
 + * 2. Redistributions in binary form must reproduce the above copyright
 + *    notice, this list of conditions and the following disclaimer in the
 + *    documentation and/or other materials provided with the distribution.
 + *
 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 + * SUCH DAMAGE.
 + *
 + * OpenRD-Client/Ultimate Device Tree Source.
 + *
 + * $FreeBSD$
 + */
 +
 +/dts-v1/;
 +
 +/ {
 +	model = "mrvl,OpenRD-CL";
 +	compatible = "OpenRD-CL";
 +	#address-cells = <1>;
 +	#size-cells = <1>;
 +
 +	aliases {
 +		ethernet0 = &enet0;
 +		ethernet1 = &enet1;
 +		mpp = &MPP;
 +		pci0 = &pci0;
 +		serial0 = &serial0;
 +		serial1 = &serial1;
 +		soc = &SOC;
 +		sram = &SRAM;
 +	};
 +
 +	cpus {
 +		#address-cells = <1>;
 +		#size-cells = <0>;
 +
 +		cpu@0 {
 +			device_type = "cpu";
 +			compatible = "ARM,88FR131";
 +			reg = <0x0>;
 +			d-cache-line-size = <32>;	// 32 bytes
 +			i-cache-line-size = <32>;	// 32 bytes
 +			d-cache-size = <0x4000>;	// L1, 16K
 +			i-cache-size = <0x4000>;	// L1, 16K
 +			timebase-frequency = <0>;
 +			bus-frequency = <0>;
 +			clock-frequency = <0>;
 +		};
 +	};
 +
 +	memory {
 +		device_type = "memory";
 +		reg = <0x0 0x20000000>;		// 512M at 0x0
 +	};
 +
 +	localbus@f1000000 {
 +		#address-cells = <2>;
 +		#size-cells = <1>;
 +		compatible = "mrvl,lbc";
 +
 +		/* This reflects CPU decode windows setup. */
 +		ranges = <0x0 0x0f 0xf9300000 0x00100000
 +			  0x1 0x1e 0xfa000000 0x00100000
 +			  0x2 0x1d 0xfa100000 0x02000000
 +			  0x3 0x1b 0xfc100000 0x00000400>;
 +
 +		nor@0,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "cfi-flash";
 +			reg = <0x0 0x0 0x00100000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +		};
 +
 +		led@1,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "led";
 +			reg = <0x1 0x0 0x00100000>;
 +		};
 +
 +		nor@2,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "cfi-flash";
 +			reg = <0x2 0x0 0x02000000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +		};
 +
 +		nand@3,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			reg = <0x3 0x0 0x00100000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +		};
 +	};
 +
 +	SOC: soc88f6281@f1000000 {
 +		#address-cells = <1>;
 +		#size-cells = <1>;
 +		compatible = "simple-bus";
 +		ranges = <0x0 0xf1000000 0x00100000>;
 +		bus-frequency = <0>;
 +
 +		PIC: pic@20200 {
 +			interrupt-controller;
 +			#address-cells = <0>;
 +			#interrupt-cells = <1>;
 +			reg = <0x20200 0x3c>;
 +			compatible = "mrvl,pic";
 +		};
 +
 +		timer@20300 {
 +			compatible = "mrvl,timer";
 +			reg = <0x20300 0x30>;
 +			interrupts = <1>;
 +			interrupt-parent = <&PIC>;
 +			mrvl,has-wdt;
 +		};
 +
 +		MPP: mpp@10000 {
 +			#pin-cells = <2>;
 +			compatible = "mrvl,mpp";
 +			reg = <0x10000 0x34>;
 +			pin-count = <50>;
 +			pin-map = <
 +				0  1		/* MPP[0]:  NF_IO[2] */
 +				1  1		/* MPP[1]:  NF_IO[3] */
 +				2  1		/* MPP[2]:  NF_IO[4] */
 +				3  1		/* MPP[3]:  NF_IO[5] */
 +				4  1		/* MPP[4]:  NF_IO[6] */
 +				5  1		/* MPP[5]:  NF_IO[7] */
 +				6  1		/* MPP[6]:  SYSRST_OUTn */
 +				8  2		/* MPP[8]:  UA0_RTS */
 +				9  2		/* MPP[9]:  UA0_CTS */
 +				10 3		/* MPP[10]: UA0_TXD */
 +				11 3		/* MPP[11]: UA0_RXD */
 +				12 1		/* MPP[12]: SD_CLK */
 +				13 1		/* MPP[13]: SD_CMD */
 +				14 1		/* MPP[14]: SD_D[0] */
 +				15 1		/* MPP[15]: SD_D[1] */
 +				16 1		/* MPP[16]: SD_D[2] */
 +				17 1		/* MPP[17]: SD_D[3] */
 +				20 3            /* MPP[20]: GE1_CPU_RX0 */
 +				21 3            /* MPP[21]: GE1_CPU_RX1 */
 +				22 3            /* MPP[22]: GE1_CPU_RX2 */
 +				23 3            /* MPP[23]: GE1_CPU_RX3 */
 +				24 3            /* MPP[24]: GE1_CPU_TX0 */
 +				25 3            /* MPP[25]: GE1_CPU_TX1 */
 +				26 3            /* MPP[26]: GE1_CPU_TX2 */
 +				27 3            /* MPP[27]: GE1_CPU_RD3 */
 +				28 0            /* MPP[28]: GPIO */
 +				29 0            /* MPP[29]: GPIO */
 +				30 3            /* GE1_RXCTL */
 +				31 3            /* GE1_RXCLK */
 +				32 3            /* GE1_TXCLK */
 +				33 3            /* GE1_TXCTL */
 +				34 0 >;         /* MPP[34]: GPIO */
 +		};
 +
 +		GPIO: gpio@10100 {
 +			#gpio-cells = <3>;
 +			compatible = "mrvl,gpio";
 +			reg = <0x10100 0x20>;
 +			gpio-controller;
 +			interrupts = <35 36 37 38 39 40 41>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		rtc@10300 {
 +			compatible = "mrvl,rtc";
 +			reg = <0x10300 0x08>;
 +		};
 +
 +		twsi@11000 {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			compatible = "mrvl,twsi";
 +			reg = <0x11000 0x20>;
 +			interrupts = <43>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		enet0: ethernet@72000 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			model = "V2";
 +			compatible = "mrvl,ge";
 +			reg = <0x72000 0x2000>;
 +			ranges = <0x0 0x72000 0x2000>;
 +			local-mac-address = [ 00 00 00 00 00 00 ];
 +			interrupts = <12 13 14 11 46>;
 +			interrupt-parent = <&PIC>;
 +			phy-handle = <&phy0>;
 +
 +			mdio@0 {
 +				#address-cells = <1>;
 +				#size-cells = <0>;
 +				compatible = "mrvl,mdio";
 +
 +				phy0: ethernet-phy@0 {
 +					reg = <0x0>;
 +				};
 +				phy1: ethernet-phy@1 {
 +					reg = <0x1>;
 +				};
 +			};
 +		};
 +
 +		enet1: ethernet@76000 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			model = "V2";
 +			compatible = "mrvl,ge";
 +			reg = <0x76000 0x2000>;
 +			ranges = <0x0 0x76000 0x2000>;
 +			local-mac-address = [ 00 00 00 00 00 00 ];
 +			interrupts = <16 17 18 15 47>;
 +			interrupt-parent = <&PIC>;
 +			phy-handle = <&phy1>;
 +		};
 +
 +		serial0: serial@12000 {
 +			compatible = "ns16550";
 +			reg = <0x12000 0x20>;
 +			reg-shift = <2>;
 +			clock-frequency = <0>;
 +			interrupts = <33>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		serial1: serial@12100 {
 +			compatible = "ns16550";
 +			reg = <0x12100 0x20>;
 +			reg-shift = <2>;
 +			clock-frequency = <0>;
 +			interrupts = <34>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		crypto@30000 {
 +			compatible = "mrvl,cesa";
 +			reg = <0x30000 0x10000>;
 +			interrupts = <22>;
 +			interrupt-parent = <&PIC>;
 +			sram-handle = <&SRAM>;
 +		};
 +
 +		usb@50000 {
 +			compatible = "mrvl,usb-ehci", "usb-ehci";
 +			reg = <0x50000 0x1000>;
 +			interrupts = <48 19>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		xor@60000 {
 +			compatible = "mrvl,xor";
 +			reg = <0x60000 0x1000>;
 +			interrupts = <5 6 7 8>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		sata@80000 {
 +			compatible = "mrvl,sata";
 +			reg = <0x80000 0x6000>;
 +			interrupts = <21>;
 +			interrupt-parent = <&PIC>;
 +		};
 +	};
 +
 +	SRAM: sram@fd000000 {
 +		compatible = "mrvl,cesa-sram";
 +		reg = <0xfd000000 0x00100000>;
 +	};
 +
 +	chosen {
 +		stdin  = "serial0";
 +		stdout = "serial0";
 +	};
 +
 +	pci0: pcie@f1040000 {
 +		compatible = "mrvl,pcie";
 +		device_type = "pci";
 +		#interrupt-cells = <1>;
 +		#size-cells = <2>;
 +		#address-cells = <3>;
 +		reg = <0xf1040000 0x2000>;
 +		bus-range = <0 255>;
 +		ranges = <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x04000000
 +			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
 +		clock-frequency = <33333333>;
 +		interrupt-parent = <&PIC>;
 +		interrupts = <44>;
 +		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 +		interrupt-map = <
 +			/* IDSEL 0x1 */
 +			0x0800 0x0 0x0 0x1 &PIC 0x9
 +			0x0800 0x0 0x0 0x2 &PIC 0x9
 +			0x0800 0x0 0x0 0x3 &PIC 0x9
 +			0x0800 0x0 0x0 0x4 &PIC 0x9
 +			>;
 +		pcie@0 {
 +			reg = <0x0 0x0 0x0 0x0 0x0>;
 +			#size-cells = <2>;
 +			#address-cells = <3>;
 +			device_type = "pci";
 +			ranges = <0x02000000 0x0 0xf4000000
 +				  0x02000000 0x0 0xf4000000
 +				  0x0 0x04040000
 +
 +				  0x01000000 0x0 0x0
 +				  0x01000000 0x0 0x0
 +				  0x0 0x00100000>;
 +		};
 +	};
 +};
 +
 
 --G4iJoqBmSsgzjUCe--
Responsible-Changed-From-To: freebsd-arm->hrs 
Responsible-Changed-By: hrs 
Responsible-Changed-When: Fri Aug 3 05:58:30 UTC 2012 
Responsible-Changed-Why:  
I'll take this. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=156814 

From: Kristof Provost <kristof@sigsegv.be>
To: bug-followup@FreeBSD.org, vancorte@biologie.ens.fr, hrs@FreeBSD.org,
	freebsd-arm@FreeBSD.org
Cc:  
Subject: Re: arm/156814: OpenRD Ultimate does not boot on DB-88F6XXX or
 SHEEVAPLUG kernel configurations
Date: Sat, 27 Oct 2012 12:26:42 +0200

 --7uYPyRQQ5N0D02nI
 Content-Type: text/plain; charset=utf-8
 Content-Disposition: inline
 
 Hi,
 
 Here's my latest config/dts for for the OpenRD board.
 
 In this version both ethernet interfaces, the CESA crypto
 accelerator and NAND work.
 
 Regards,
 Kristof Provost
 
 
 --7uYPyRQQ5N0D02nI
 Content-Type: text/x-diff; charset=utf-8
 Content-Disposition: attachment; filename="openrd-cl.patch"
 
 commit ee306161ffe5acfa6d43c712b37fd04f843db4f1
 Author: Kristof Provost <Kristof@codepro.be>
 Date:   Fri Oct 26 21:24:03 2012 +0000
 
     Add OpenRD support.
 
 diff --git a/sys/arm/conf/OPENRD-CL b/sys/arm/conf/OPENRD-CL
 new file mode 100644
 index 0000000..8f6931e
 --- /dev/null
 +++ b/sys/arm/conf/OPENRD-CL
 @@ -0,0 +1,101 @@
 +#
 +# Custom kernel for OpenRD Client/Ultimate devices.
 +#
 +# $FreeBSD$
 +#
 +
 +ident		OPENRD-CL
 +include		"../mv/kirkwood/std.sheevaplug"
 +
 +options		SOC_MV_KIRKWOOD
 +makeoptions	MODULES_OVERRIDE=""
 +
 +makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
 +makeoptions	WERROR="-Werror"
 +
 +
 +options		SCHED_4BSD		#4BSD scheduler
 +options		INET			#InterNETworking
 +options		INET6			#IPv6 communications protocols
 +options		FFS			#Berkeley Fast Filesystem
 +options		NANDFS			#NAND Filesystem
 +options		NFSCL			#New Network Filesystem Client
 +options		NFSLOCKD		#Network Lock Manager
 +options		NFS_ROOT		#NFS usable as /, requires NFSCL
 +options		BOOTP
 +options		BOOTP_NFSROOT
 +options		BOOTP_NFSV3
 +options		BOOTP_WIRED_TO=mge0
 +
 +options		PROCFS			# Process filesystem (requires PSEUDOFS)
 +options		PSEUDOFS		# Pseudo-filesystem framework
 +
 +# Root fs on USB device
 +#options	ROOTDEVNAME=\"ufs:/dev/da0a\"
 +# Root fs on NAND
 +#options	ROOTDEVNAME=\"nandfd:/dev/gnand0s.rootfs\"
 +
 +options		SYSVSHM			#SYSV-style shared memory
 +options		SYSVMSG			#SYSV-style message queues
 +options		SYSVSEM			#SYSV-style semaphores
 +options		_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
 +options		MUTEX_NOINLINE
 +options		RWLOCK_NOINLINE
 +options		NO_FFS_SNAPSHOT
 +options		NO_SWAPPING
 +
 +# Debugging
 +options		ALT_BREAK_TO_DEBUGGER
 +options		DDB
 +options		KDB
 +options		DEADLKRES		# Enable the deadlock resolver
 +makeoptions	INVARIANTS
 +options		INVARIANTS		# Enable calls of extra sanity checking
 +options		INVARIANT_SUPPORT	# Extra sanity checks of internal structures, required by INVARIANTS
 +options		WITNESS			# Enable checks to detect deadlocks and cycles
 +options		WITNESS_SKIPSPIN	# Don't run witness on spinlocks for speed
 +
 +# Pseudo devices
 +device		random
 +device		pty
 +device		loop
 +
 +# Serial ports
 +device		uart
 +
 +# Networking
 +device		ether
 +device		mge			# Marvell Gigabit Ethernet controller
 +device		mii
 +device		e1000phy
 +device		bpf
 +options		HZ=1000
 +options		DEVICE_POLLING
 +device		vlan
 +
 +device		cesa			# Marvell security engine
 +device		crypto
 +device		cryptodev
 +
 +# NAND
 +makeoptions	WITH_NAND="yes"
 +
 +device		nand
 +device		nandsim
 +options		ALQ
 +options		KTR_ALQ
 +
 +# USB
 +options		USB_DEBUG	# enable debug msgs
 +device		usb
 +device		ehci
 +device		umass
 +device		scbus
 +device		pass
 +device		da
 +
 +# Flattened Device Tree
 +options		FDT
 +options		FDT_DTB_STATIC
 +makeoptions	FDT_DTS_FILE=openrd-cl.dts
 +
 diff --git a/sys/boot/fdt/dts/openrd-cl.dts b/sys/boot/fdt/dts/openrd-cl.dts
 new file mode 100644
 index 0000000..48386ff
 --- /dev/null
 +++ b/sys/boot/fdt/dts/openrd-cl.dts
 @@ -0,0 +1,332 @@
 +/*
 + * Copyright (c) 2009-2010 The FreeBSD Foundation
 + * All rights reserved.
 + *
 + * This software was developed by Semihalf under sponsorship from
 + * the FreeBSD Foundation.
 + *
 + * Redistribution and use in source and binary forms, with or without
 + * modification, are permitted provided that the following conditions
 + * are met:
 + * 1. Redistributions of source code must retain the above copyright
 + *    notice, this list of conditions and the following disclaimer.
 + * 2. Redistributions in binary form must reproduce the above copyright
 + *    notice, this list of conditions and the following disclaimer in the
 + *    documentation and/or other materials provided with the distribution.
 + *
 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 + * SUCH DAMAGE.
 + *
 + * OpenRD-Client/Ultimate Device Tree Source.
 + *
 + * $FreeBSD$
 + */
 +
 +/dts-v1/;
 +
 +/ {
 +	model = "mrvl,OpenRD-CL";
 +	compatible = "OpenRD-CL";
 +	#address-cells = <1>;
 +	#size-cells = <1>;
 +
 +	aliases {
 +		ethernet0 = &enet0;
 +		ethernet1 = &enet1;
 +		mpp = &MPP;
 +		pci0 = &pci0;
 +		serial0 = &serial0;
 +		serial1 = &serial1;
 +		soc = &SOC;
 +		sram = &SRAM;
 +	};
 +
 +	cpus {
 +		#address-cells = <1>;
 +		#size-cells = <0>;
 +
 +		cpu@0 {
 +			device_type = "cpu";
 +			compatible = "ARM,88FR131";
 +			reg = <0x0>;
 +			d-cache-line-size = <32>;	// 32 bytes
 +			i-cache-line-size = <32>;	// 32 bytes
 +			d-cache-size = <0x4000>;	// L1, 16K
 +			i-cache-size = <0x4000>;	// L1, 16K
 +			timebase-frequency = <0>;
 +			bus-frequency = <0>;
 +			clock-frequency = <0>;
 +		};
 +	};
 +
 +	memory {
 +		device_type = "memory";
 +		reg = <0x0 0x20000000>;		// 512M at 0x0
 +	};
 +
 +	localbus@0 {
 +		#address-cells = <2>;
 +		#size-cells = <1>;
 +		compatible = "mrvl,lbc";
 +		bank-count = <3>;
 +
 +		/* This reflects CPU decode windows setup. */
 +		ranges = <0x0 0x2f 0xf9300000 0x00100000>;
 +
 +		nand@0,0 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			compatible = "mrvl,nfc";
 +			reg = <0x0 0x0 0x00100000>;
 +			bank-width = <2>;
 +			device-width = <1>;
 +
 +			partition@0 {
 +				label = "u-boot";
 +				reg = <0x0 0x100000>;
 +				read-only;
 +			};
 +
 +			partition@100000 {
 +				label = "kernel";
 +				reg = <0x100000 0x400000>;
 +			};
 +
 +			partition@500000 {
 +				label = "rootfs";
 +				reg = <0x700000 0x1f000000>;
 +			};
 +		};
 +	};
 +
 +	SOC: soc88f6281@f1000000 {
 +		#address-cells = <1>;
 +		#size-cells = <1>;
 +		compatible = "simple-bus";
 +		ranges = <0x0 0xf1000000 0x00100000>;
 +		bus-frequency = <0>;
 +
 +		PIC: pic@20200 {
 +			interrupt-controller;
 +			#address-cells = <0>;
 +			#interrupt-cells = <1>;
 +			reg = <0x20200 0x3c>;
 +			compatible = "mrvl,pic";
 +		};
 +
 +		timer@20300 {
 +			compatible = "mrvl,timer";
 +			reg = <0x20300 0x30>;
 +			interrupts = <1>;
 +			interrupt-parent = <&PIC>;
 +			mrvl,has-wdt;
 +		};
 +
 +		MPP: mpp@10000 {
 +			#pin-cells = <2>;
 +			compatible = "mrvl,mpp";
 +			reg = <0x10000 0x34>;
 +			pin-count = <50>;
 +			pin-map = <
 +				0  1		/* MPP[0]:  NF_IO[2] */
 +				1  1		/* MPP[1]:  NF_IO[3] */
 +				2  1		/* MPP[2]:  NF_IO[4] */
 +				3  1		/* MPP[3]:  NF_IO[5] */
 +				4  1		/* MPP[4]:  NF_IO[6] */
 +				5  1		/* MPP[5]:  NF_IO[7] */
 +				6  1		/* MPP[6]:  SYSRST_OUTn */
 +				8  2		/* MPP[8]:  UA0_RTS */
 +				9  2		/* MPP[9]:  UA0_CTS */
 +				10 3		/* MPP[10]: UA0_TXD */
 +				11 3		/* MPP[11]: UA0_RXD */
 +				12 1		/* MPP[12]: SD_CLK */
 +				13 1		/* MPP[13]: SD_CMD */
 +				14 1		/* MPP[14]: SD_D[0] */
 +				15 1		/* MPP[15]: SD_D[1] */
 +				16 1		/* MPP[16]: SD_D[2] */
 +				17 1		/* MPP[17]: SD_D[3] */
 +				18 1		/* MPP[18]: NF_IO[0] */
 +				19 1		/* MPP[19]: NF_IO[1] */
 +				20 3            /* MPP[20]: GE1_CPU_RX0 */
 +				21 3            /* MPP[21]: GE1_CPU_RX1 */
 +				22 3            /* MPP[22]: GE1_CPU_RX2 */
 +				23 3            /* MPP[23]: GE1_CPU_RX3 */
 +				24 3            /* MPP[24]: GE1_CPU_TX0 */
 +				25 3            /* MPP[25]: GE1_CPU_TX1 */
 +				26 3            /* MPP[26]: GE1_CPU_TX2 */
 +				27 3            /* MPP[27]: GE1_CPU_RD3 */
 +				28 0            /* MPP[28]: GPIO */
 +				29 0            /* MPP[29]: GPIO */
 +				30 3            /* GE1_RXCTL */
 +				31 3            /* GE1_RXCLK */
 +				32 3            /* GE1_TXCLK */
 +				33 3            /* GE1_TXCTL */
 +				34 0 >;         /* MPP[34]: GPIO */
 +		};
 +
 +		GPIO: gpio@10100 {
 +			#gpio-cells = <3>;
 +			compatible = "mrvl,gpio";
 +			reg = <0x10100 0x20>;
 +			gpio-controller;
 +			interrupts = <35 36 37 38 39 40 41>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		rtc@10300 {
 +			compatible = "mrvl,rtc";
 +			reg = <0x10300 0x08>;
 +		};
 +
 +		twsi@11000 {
 +			#address-cells = <1>;
 +			#size-cells = <0>;
 +			compatible = "mrvl,twsi";
 +			reg = <0x11000 0x20>;
 +			interrupts = <43>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		enet0: ethernet@72000 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			model = "V2";
 +			compatible = "mrvl,ge";
 +			reg = <0x72000 0x2000>;
 +			ranges = <0x0 0x72000 0x2000>;
 +			local-mac-address = [ 00 00 00 00 00 00 ];
 +			interrupts = <12 13 14 11 46>;
 +			interrupt-parent = <&PIC>;
 +			phy-handle = <&phy0>;
 +
 +			mdio@0 {
 +				#address-cells = <1>;
 +				#size-cells = <0>;
 +				compatible = "mrvl,mdio";
 +
 +				phy0: ethernet-phy@0 {
 +					reg = <0x0>;
 +				};
 +				phy1: ethernet-phy@1 {
 +					reg = <0x1>;
 +				};
 +			};
 +		};
 +
 +		enet1: ethernet@76000 {
 +			#address-cells = <1>;
 +			#size-cells = <1>;
 +			model = "V2";
 +			compatible = "mrvl,ge";
 +			reg = <0x76000 0x2000>;
 +			ranges = <0x0 0x76000 0x2000>;
 +			local-mac-address = [ 00 00 00 00 00 00 ];
 +			interrupts = <16 17 18 15 47>;
 +			interrupt-parent = <&PIC>;
 +			phy-handle = <&phy1>;
 +		};
 +
 +		serial0: serial@12000 {
 +			compatible = "ns16550";
 +			reg = <0x12000 0x20>;
 +			reg-shift = <2>;
 +			clock-frequency = <0>;
 +			interrupts = <33>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		serial1: serial@12100 {
 +			compatible = "ns16550";
 +			reg = <0x12100 0x20>;
 +			reg-shift = <2>;
 +			clock-frequency = <0>;
 +			interrupts = <34>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		crypto@30000 {
 +			compatible = "mrvl,cesa";
 +			reg = <0x30000 0x10000>;
 +			interrupts = <22>;
 +			interrupt-parent = <&PIC>;
 +			sram-handle = <&SRAM>;
 +		};
 +
 +		usb@50000 {
 +			compatible = "mrvl,usb-ehci", "usb-ehci";
 +			reg = <0x50000 0x1000>;
 +			interrupts = <48 19>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		xor@60000 {
 +			compatible = "mrvl,xor";
 +			reg = <0x60000 0x1000>;
 +			interrupts = <5 6 7 8>;
 +			interrupt-parent = <&PIC>;
 +		};
 +
 +		sata@80000 {
 +			compatible = "mrvl,sata";
 +			reg = <0x80000 0x6000>;
 +			interrupts = <21>;
 +			interrupt-parent = <&PIC>;
 +		};
 +	};
 +
 +	SRAM: sram@fd000000 {
 +		compatible = "mrvl,cesa-sram";
 +		reg = <0xfd000000 0x00100000>;
 +	};
 +
 +	chosen {
 +		stdin  = "serial0";
 +		stdout = "serial0";
 +	};
 +
 +	pci0: pcie@f1040000 {
 +		compatible = "mrvl,pcie";
 +		device_type = "pci";
 +		#interrupt-cells = <1>;
 +		#size-cells = <2>;
 +		#address-cells = <3>;
 +		reg = <0xf1040000 0x2000>;
 +		bus-range = <0 255>;
 +		ranges = <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x04000000
 +			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
 +		clock-frequency = <33333333>;
 +		interrupt-parent = <&PIC>;
 +		interrupts = <44>;
 +		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 +		interrupt-map = <
 +			/* IDSEL 0x1 */
 +			0x0800 0x0 0x0 0x1 &PIC 0x9
 +			0x0800 0x0 0x0 0x2 &PIC 0x9
 +			0x0800 0x0 0x0 0x3 &PIC 0x9
 +			0x0800 0x0 0x0 0x4 &PIC 0x9
 +			>;
 +		pcie@0 {
 +			reg = <0x0 0x0 0x0 0x0 0x0>;
 +			#size-cells = <2>;
 +			#address-cells = <3>;
 +			device_type = "pci";
 +			ranges = <0x02000000 0x0 0xf4000000
 +				  0x02000000 0x0 0xf4000000
 +				  0x0 0x04040000
 +
 +				  0x01000000 0x0 0x0
 +				  0x01000000 0x0 0x0
 +				  0x0 0x00100000>;
 +		};
 +	};
 +};
 +
 
 --7uYPyRQQ5N0D02nI--
>Unformatted:
