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Date: Thu, 12 Nov 2009 15:47:17 GMT
From: Steve Polyack <spolyack@collaborativefusion.com>
To: freebsd-gnats-submit@FreeBSD.org
Subject: Invalid freq for Enhanced Speedstep on Intel(R) Xeon(R) CPU E5506
X-Send-Pr-Version: www-3.1
X-GNATS-Notify:

>Number:         140506
>Category:       amd64
>Synopsis:       [est] Invalid freq for Enhanced Speedstep on Intel(R) Xeon(R) CPU E5506
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    mav
>State:          closed
>Quarter:        
>Keywords:       
>Date-Required:  
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Thu Nov 12 15:50:01 UTC 2009
>Closed-Date:    Thu Nov 26 15:12:22 UTC 2009
>Last-Modified:  Thu Nov 26 15:20:05 UTC 2009
>Originator:     Steve Polyack
>Release:        9-CURRENT (11/11/2009)
>Organization:
Collaborative Fusion, Inc.
>Environment:
FreeBSD #### 9.0-CURRENT FreeBSD 9.0-CURRENT #2: Wed Nov 11 14:52:42 EST 2009     root@####:/usr/obj/zstore/src/sys/####  amd64

>Description:
Various enhanced speedstep states reported by the processor are marked as invalid by FreeBSD during boot:
# dmesg | egrep ^est 
est0: <Enhanced SpeedStep Frequency Control> on cpu0
est0: Invalid id16 (set, cur) = (15, 16)
est0: Invalid freq 2000, ignored.
est0: Invalid id16 (set, cur) = (14, 16)
est0: Invalid freq 1867, ignored.
est0: Invalid id16 (set, cur) = (13, 16)
est0: Invalid freq 1733, ignored.
est0: Invalid id16 (set, cur) = (12, 16)
est0: Invalid freq 1600, ignored.
est1: <Enhanced SpeedStep Frequency Control> on cpu1
est1: Invalid id16 (set, cur) = (15, 16)
est1: Invalid freq 2000, ignored.
est1: Invalid id16 (set, cur) = (14, 16)
est1: Invalid freq 1867, ignored.
est1: Invalid id16 (set, cur) = (13, 16)
est1: Invalid freq 1733, ignored.
est1: Invalid id16 (set, cur) = (12, 16)
est1: Invalid freq 1600, ignored.
est2: <Enhanced SpeedStep Frequency Control> on cpu2
est2: Invalid id16 (set, cur) = (15, 16)
est2: Invalid freq 2000, ignored.
est2: Invalid id16 (set, cur) = (14, 16)
est2: Invalid freq 1867, ignored.
est2: Invalid id16 (set, cur) = (13, 16)
est2: Invalid freq 1733, ignored.
est2: Invalid id16 (set, cur) = (12, 16)
est2: Invalid freq 1600, ignored.
est3: <Enhanced SpeedStep Frequency Control> on cpu3
est3: Invalid id16 (set, cur) = (15, 16)
est3: Invalid freq 2000, ignored.
est3: Invalid id16 (set, cur) = (14, 16)
est3: Invalid freq 1867, ignored.
est3: Invalid id16 (set, cur) = (13, 16)
est3: Invalid freq 1733, ignored.
est3: Invalid id16 (set, cur) = (12, 16)
est3: Invalid freq 1600, ignored.

# sysctl dev.est
dev.est.0.%desc: Enhanced SpeedStep Frequency Control
dev.est.0.%driver: est
dev.est.0.%parent: cpu0
dev.est.0.freq_settings: 2133/80000
dev.est.1.%desc: Enhanced SpeedStep Frequency Control
dev.est.1.%driver: est
dev.est.1.%parent: cpu1
dev.est.1.freq_settings: 2133/80000
dev.est.2.%desc: Enhanced SpeedStep Frequency Control
dev.est.2.%driver: est
dev.est.2.%parent: cpu2
dev.est.2.freq_settings: 2133/80000
dev.est.3.%desc: Enhanced SpeedStep Frequency Control
dev.est.3.%driver: est
dev.est.3.%parent: cpu3
dev.est.3.freq_settings: 2133/80000

# sysctl dev.cpu
dev.cpu.0.%desc: ACPI CPU
dev.cpu.0.%driver: cpu
dev.cpu.0.%location: handle=\_PR_.P001
dev.cpu.0.%pnpinfo: _HID=none _UID=0
dev.cpu.0.%parent: acpi0
dev.cpu.0.freq: 2133
dev.cpu.0.freq_levels: 2133/80000 1866/70000 1599/60000 1333/50000 1066/40000 799/30000 533/20000 266/10000
dev.cpu.0.cx_supported: C1/3 C2/205 C3/245
dev.cpu.0.cx_lowest: C1
dev.cpu.0.cx_usage: 100.00% 0.00% 0.00% last 500us
dev.cpu.1.%desc: ACPI CPU
dev.cpu.1.%driver: cpu
dev.cpu.1.%location: handle=\_PR_.P002
dev.cpu.1.%pnpinfo: _HID=none _UID=0
dev.cpu.1.%parent: acpi0
dev.cpu.1.cx_supported: C1/3 C2/205 C3/245
dev.cpu.1.cx_lowest: C1
dev.cpu.1.cx_usage: 100.00% 0.00% 0.00% last 500us
dev.cpu.2.%desc: ACPI CPU
dev.cpu.2.%driver: cpu
dev.cpu.2.%location: handle=\_PR_.P003
dev.cpu.2.%pnpinfo: _HID=none _UID=0
dev.cpu.2.%parent: acpi0
dev.cpu.2.cx_supported: C1/3 C2/205 C3/245
dev.cpu.2.cx_lowest: C1
dev.cpu.2.cx_usage: 100.00% 0.00% 0.00% last 500us
dev.cpu.3.%desc: ACPI CPU
dev.cpu.3.%driver: cpu
dev.cpu.3.%location: handle=\_PR_.P004
dev.cpu.3.%pnpinfo: _HID=none _UID=0
dev.cpu.3.%parent: acpi0
dev.cpu.3.cx_supported: C1/3 C2/205 C3/245
dev.cpu.3.cx_lowest: C1
dev.cpu.3.cx_usage: 100.00% 0.00% 0.00% last 500us

dmesg:
CPU: Intel(R) Xeon(R) CPU           E5506  @ 2.13GHz (2133.42-MHz K8-class CPU)
  Origin = "GenuineIntel"  Id = 0x106a5  Stepping = 5
Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>  Features2=0x9ce3bd<SSE3,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,DCA,SSE4.1,SSE4.2,POPCNT>
  AMD Features=0x28100800<SYSCALL,NX,RDTSCP,LM>
  AMD Features2=0x1<LAHF>
  TSC: P-state invariant

The motherboard is a SuperMicro MBD-X8DTL-iF-O Dual LGA 1366 Intel 5500.

>How-To-Repeat:
Get a LGA 1366 motherboard, an Intel Xeon E5506 CPU, and install 9-CURRENT!  I'm unsure if 8.0-RC2 or 7-STABLE report the same thing.
>Fix:


>Release-Note:
>Audit-Trail:
State-Changed-From-To: open->patched 
State-Changed-By: mav 
State-Changed-When: Sat Nov 14 16:48:16 UTC 2009 
State-Changed-Why:  
I've just committed patch to HEAD to address this issue. 


Responsible-Changed-From-To: freebsd-amd64->mav 
Responsible-Changed-By: mav 
Responsible-Changed-When: Sat Nov 14 16:48:16 UTC 2009 
Responsible-Changed-Why:  
I've just committed patch to HEAD to address this issue. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=140506 

From: Steve Polyack <spolyack@collaborativefusion.com>
To: bug-followup@FreeBSD.org, spolyack@collaborativefusion.com
Cc:  
Subject: Re: amd64/140506: [est] Invalid freq for Enhanced Speedstep on Intel(R)
 Xeon(R) CPU E5506
Date: Mon, 16 Nov 2009 16:07:07 -0500

 The messages during boot have changed and now report:
 est0: <Enhanced SpeedStep Frequency Control> on cpu0
 est0: Invalid id16 (set, cur) = (15, 16)
 est0: Can't check freq 2000, it may be invalid
 est0: Invalid id16 (set, cur) = (14, 16)
 est0: Can't check freq 1867, it may be invalid
 est0: Invalid id16 (set, cur) = (13, 16)
 est0: Can't check freq 1733, it may be invalid
 est0: Invalid id16 (set, cur) = (12, 16)
 est0: Can't check freq 1600, it may be invalid
 
 However, the issues seems to be fixed as the est devices now report 
 additional freq_settings:
 $ sysctl dev.est     
 dev.est.0.%desc: Enhanced SpeedStep Frequency Control
 dev.est.0.%driver: est
 dev.est.0.%parent: cpu0
 dev.est.0.freq_settings: 2133/80000 2000/66000 1867/56000 1733/47000 
 1600/39000
 dev.est.1.%desc: Enhanced SpeedStep Frequency Control
 dev.est.1.%driver: est
 dev.est.1.%parent: cpu1
 dev.est.1.freq_settings: 2133/80000 2000/66000 1867/56000 1733/47000 
 1600/39000
 dev.est.2.%desc: Enhanced SpeedStep Frequency Control
 dev.est.2.%driver: est
 dev.est.2.%parent: cpu2
 dev.est.2.freq_settings: 2133/80000 2000/66000 1867/56000 1733/47000 
 1600/39000
 dev.est.3.%desc: Enhanced SpeedStep Frequency Control
 dev.est.3.%driver: est
 dev.est.3.%parent: cpu3
 dev.est.3.freq_settings: 2133/80000 2000/66000 1867/56000 1733/47000 
 1600/39000
 
 Thanks!
State-Changed-From-To: patched->closed 
State-Changed-By: mav 
State-Changed-When: Thu Nov 26 15:11:47 UTC 2009 
State-Changed-Why:  
Patch merged to 8-STABLE. 

http://www.freebsd.org/cgi/query-pr.cgi?pr=140506 

From: dfilter@FreeBSD.ORG (dfilter service)
To: bug-followup@FreeBSD.org
Cc:  
Subject: Re: amd64/140506: commit references a PR
Date: Thu, 26 Nov 2009 15:11:33 +0000 (UTC)

 Author: mav
 Date: Thu Nov 26 15:11:19 2009
 New Revision: 199834
 URL: http://svn.freebsd.org/changeset/base/199834
 
 Log:
   MFC r199268, r199269, r199273:
   Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU
   core, only pair of them. As result, both cores are running on highest
   one of requested frequencies, and that is reported by status register.
   Such behavior confuses frequency validation logic, as it runs on only
   one core, as SMP is not yet launched, making EIST completely unusable.
   
   Disable frequency validation by default, for systems with more then one
   CPU, until we can implement it properly. It looks like making more harm
   now then benefits. Add 'hw.est.strict' loader tunable to control it.
   
   PR:		amd64/140506
 
 Modified:
   stable/8/sys/i386/cpufreq/est.c
 Directory Properties:
   stable/8/sys/   (props changed)
   stable/8/sys/amd64/include/xen/   (props changed)
   stable/8/sys/cddl/contrib/opensolaris/   (props changed)
   stable/8/sys/contrib/dev/acpica/   (props changed)
   stable/8/sys/contrib/pf/   (props changed)
   stable/8/sys/dev/xen/xenpci/   (props changed)
 
 Modified: stable/8/sys/i386/cpufreq/est.c
 ==============================================================================
 --- stable/8/sys/i386/cpufreq/est.c	Thu Nov 26 14:56:58 2009	(r199833)
 +++ stable/8/sys/i386/cpufreq/est.c	Thu Nov 26 15:11:19 2009	(r199834)
 @@ -96,6 +96,8 @@ struct est_softc {
  
  static int msr_info_enabled = 0;
  TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
 +static int strict = -1;
 +TUNABLE_INT("hw.est.strict", &strict);
  
  /* Default bus clock value for Centrino processors. */
  #define INTEL_BUS_CLK		100
 @@ -1025,6 +1027,9 @@ est_attach(device_t dev)
  	sc = device_get_softc(dev);
  	sc->dev = dev;
  
 +	/* On SMP system we can't guarantie independent freq setting. */
 +	if (strict == -1 && mp_ncpus > 1)
 +		strict = 0;
  	/* Check CPU for supported settings. */
  	if (est_get_info(dev))
  		return (ENXIO);
 @@ -1119,17 +1124,21 @@ est_acpi_info(device_t dev, freq_info **
  		 */
  		if (sets[i].freq > 0) {
  			error = est_set_id16(dev, sets[i].spec[0], 1);
 -			if (error != 0) {
 +			if (error != 0 && strict) {
  				if (bootverbose) 
  					device_printf(dev, "Invalid freq %u, "
  					    "ignored.\n", sets[i].freq);
 -			} else {
 -				table[j].freq = sets[i].freq;
 -				table[j].volts = sets[i].volts;
 -				table[j].id16 = sets[i].spec[0];
 -				table[j].power = sets[i].power;
 -				++j;
 +				continue;
 +			} else if (error != 0 && bootverbose) {
 +				device_printf(dev, "Can't check freq %u, "
 +				    "it may be invalid\n",
 +				    sets[i].freq);
  			}
 +			table[j].freq = sets[i].freq;
 +			table[j].volts = sets[i].volts;
 +			table[j].id16 = sets[i].spec[0];
 +			table[j].power = sets[i].power;
 +			++j;
  		}
  	}
  	/* restore saved setting */
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>Unformatted:
