

                README FILE FOR THE HADLOP ARCHITECTURE FILE
                               sort_loop.arc
                               January, 1997

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   This architecture simulates a bitonic sorter based on perfect-shuffle
   interconnections. The input data are stored in the INPUT primitive.
   The bit vectors enter the architecture in bit-serial order. That means
   the vectors are stored in the x/z direction of the INPUT - Modify
   window. Each x/z plane contains several bit vectors (binary numbers).
   After the simulation the numbers are sorted in the x/z planes of the
   OUTPUT primitive.



   The algorithm was taken from:


   M.P.Y. Desmulliez, F.A.P. Tooley, J.A.B. Dines, N.L. Grant, D.J. Goodwill,
   D. Baillie, B.S. Wherrett, P. W. Foulk, S. Ashcroft and P. Black

   "Perfect-shuffle interconnected bitonic sorter: optoelectronic design"

   Applied Optics, Vol. 34, No. 23, 10 August 1995



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    HADLOP homepage:

    http://www2.informatik.uni-jena.de/pope/HADLOP/hadlop.html

    If you have questions send an e-mail to:

    hadlop@informatik.uni-jena.de


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