BRUSEY20 - PIC to VHDL Parser - v2.3
Copyright (C) 1996 by Tom Mayo

Brief Description
-----------------

This program is used to translate a state diagram into synthesizable
VHDL.  The state diagram may be entered with XFig, a free drawing tool.
The format which brusey20 accepts is the PIC format, which may be
exported by XFig.  Output is at least suitable for synthesis using
Exemplar's Galileo.  It may also be useful for other synthesizers.

To contact the author:  tcmayo@fang.berk.net

Tom Mayo
106 S. Hemlock Ln.
Williamstown, MA  01267

I encourage bug reports and enhancement requests!

License
-------

This program is free software; you can redistribute it and/or modify
it under the terms of version 2 of the GNU General Public License as
published by the Free Software Foundation.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

Installation for Unix
---------------------

If you retrieved a binary which will run on your platform, simply
move it to a directory in your path, for example, /usr/local/bin.
Binaries are available for Linux, SunOS, and AIX.

The documentation is in the form of a man page, brusey20.1.  This
file should be moved to a directory in your manpath, for example,
/usr/local/man/man1.

If you wish to compile a new binary, use one of the makefiles
provided.  Modify if necessary, then compile.  You need flex,
bison, and gcc, all from the GNU organization (available via
anonymous FTP from prep.ai.mit.edu).  You may be able to get it
to compile with other "lex," "yacc," and "cc" equivalents, but
I haven't tried.

Using it
--------

The first step is to draw a state diagram and export it to PIC
format.

Next, run brusey20 to generate behavioral VHDL code.

Finally, run your synthesis program to generate a netlist from
the behavioral VHDL.

Please note that VHDL code output by this program is not subject
to any restrictions and may be used for any purpose deemed fit by
the operator of the program.  To be clear with respect to the GNU
General Public License which covers the program itself, the output
of this program is not to be considered a "work derived from the
program".

There are several examples of VHDL styles brusey20 can currently
produce, and what it should be capable of in future revisions.
Currently, the woj, exemplar_a1, and new examples are supported.
They will synthesize with Exemplar's Galileo.

Documentation
-------------

Stinks.

Seriously, my thesis describes the inner workings of brusey20, and
gives some hints on how to draw state diagrams so that brusey20 can
understand them.  It is available from my web page:

http:/bcn.net/~mayo

I'm sorry, but I haven't written a user's guide yet.

--
Tom Mayo  N1RMU
