# $Id: Makefile,v 1.4 2001/03/06 09:05:58 abhijit Exp $
#
# compiler variables
#

CC	= gcc
CFLAGS	= -O -Wall

#
# local variables: functions.o is the library of functions used in other progs
#

progs		=	eep
commonobj	=	functions.o
commonhdr	=	header.h

#
# targets, dependencies, rules, and commands
#

all:	$(progs)

# adding $(commonobj) as a dependency for $(progs) causes the implicit
# command rule to change:  for every member <target> of $(progs),
# to build <target> make will run  $(CC) $(CFLAGS) -o <target> $(commonobj)

$(progs):	$(commonobj)

$(commonobj):	$(commonhdr)

.PHONY:	clean

.PHONY:	strip

clean:
	rm -f $(progs) $(commonobj)

strip:
	strip $(progs)

