/*
 * Copyright (c) 2002-2005 Endace Technology Ltd, Hamilton, New Zealand.
 * All rights reserved.
 *
 * This source code is proprietary to Endace Technology Limited and no part
 * of it may be redistributed, published or disclosed except as outlined in
 * the written contract supplied with this product.
 *
 * $Id: dagtoken.h 13608 2010-12-29 08:32:27Z karthik.sharma $
 */

enum
{
	T_ERROR = -1,
	T_ATM = 1,
	T_TEST_A,
	T_TEST_B,
	T_TEST_C,
	T_ATM_ADD_HEC,
	T_ATM_DESCRAMBLE,
	T_ATM_FIX_HEC,
	T_ATM_LCELL,
	T_ATM_NCELLS,
	T_ATM_PASS_HEC,
	T_ATM_PASS_IDLE,
	T_ATM_PLOAD_SCRAMBLE,
	T_DEFAULT,
	T_DEFAULT_DS3_ATM,
	T_DEFAULT_DS3_HDLC,
	T_DEFAULT_E3_ATM,
	T_DEFAULT_E3_HDLC,
	T_DEFAULT_E3_HDLC_FRACT,
	T_DEFAULT_KENTROX,
	T_DUCK_SET_TO_HOST,
	T_DUCK_SYNC_THRESH,
	T_ETH,
	T_ETH_10,
	T_ETH_10G,
	T_ETH_100,
	T_ETH_1000_STATUS,
	T_ETH_1000,
	T_ETH_AUTO,
	T_ETH_WAN,
	T_FF_00_DEL,
	T_GPP_ALIGN64,
	T_GPP_ENABLE_A,
	T_GPP_ENABLE_B,
	T_GPP_ENABLE_C,
	T_GPP_ENABLE_D,
    T_GPP_ENABLE_E,
    T_GPP_ENABLE_F,
    T_GPP_ENABLE_G,
    T_GPP_ENABLE_H,
    T_GPP_ENABLE_I,
    T_GPP_ENABLE_J,
    T_GPP_ENABLE_K,
    T_GPP_ENABLE_L,
    T_GPP_ENABLE_M,
    T_GPP_ENABLE_N,
    T_GPP_ENABLE_O,
    T_GPP_ENABLE_P,
	T_GPP_SLEN,
	T_RAW_SLEN,
	T_E3_CC_FRACT,
	T_GPP_VARLEN,
	T_HDLC,
	T_PPP,
	T_HEC_CORRECTION,
    T_INTERFACE_SWAP,
	T_LINK_ADM,
	T_LINK_ANALOG_LOS,
	T_LINK_AMI,
	T_LINK_ASYNC1,
	T_LINK_B8ZS,
	T_LINK_BIT_SYNC,
	T_LINK_BYTE_SYNC1,
	T_LINK_BYTE_SYNC2,
	T_LINK_CLEAR,
	T_LINK_CORE_ON,
	T_LINK_CRC,
	T_LINK_DCR,
	T_LINK_DIGITAL_LOS,
	T_LINK_DISCARD,
	T_LINK_DS3_M23,
	T_LINK_DS3_M23_PLCP,
	T_LINK_DS3_M23_IF,
	T_LINK_DS3_M23_EF,
	T_LINK_DS3_M23_FF,
	T_LINK_DS3_CBIT,
	T_LINK_DS3_CBIT_PLCP,
	T_LINK_DS3_CBIT_IF,
	T_LINK_DS3_CBIT_EF,
	T_LINK_DS3_CBIT_FF,
	T_LINK_E1_CRC,
	T_LINK_E1_UNFRAMED,
	T_LINK_E1,
	T_LINK_E3,
	T_LINK_EQL,
	T_LINK_E3_G751,
	T_LINK_E3_G751_PLCP,
	T_LINK_E3_G751_IF,
	T_LINK_E3_CC,
	T_LINK_E3_HDLC_FRACT,
	T_D37D_FRAMER_LOOPBACK,
	T_LINK_FCL,
	T_LINK_HGAIN,
	T_LINK_LASER,
	T_LINK_LSEQL,
	T_LINK_LSFCL,
	T_LINK_LT0,
	T_LINK_LT1,
	T_LINK_M23,
	T_LINK_MODE,
	T_LINK_OC1,
	T_LINK_OC3,
	T_LINK_OC12,
	T_LINK_OC48,
	T_LINK_OC192,
	T_LINK_PDH_GLOBAL,
	T_LINK_RESET,
	T_LINK_RKTIOPWR,
	T_LINK_RX_TERMEXT,
	T_LINK_SFPPWR,
	T_LINK_T1,
	T_LINK_T1_ESF,
	T_LINK_T1_SF,
	T_LINK_T1_UNFRAMED,
	T_LINK_TERM75,
	T_LINK_TERM100,
	T_LINK_TERM120,
	T_LINK_TERMEXT,
	T_LINK_TU11,
	T_LINK_TU12,
	T_LINK_TUNOMAP,
	T_LINK_TX_TERMEXT,
	T_LINK_VC3,
	T_LINK_VC4,
	T_LINK_VC4C,
	T_LINK_WHICH,
	T_LIU_LOOPBACK,
	T_MASTER,
	T_MUX_CONFIG,
	T_MUX_RXMERGE,
	T_MUX_RXSPLIT,
	T_PBM_MEMCONFIG,
	T_VDAG_MEMALLOC,
	T_VDAG_SETNODE,
	T_PBM_OVERLAP,
	T_PBM_DROP,
	T_PBM_RXONLY,
	T_PBM_RXTX,
	T_PBM_TXONLY,
	T_POS_CRC16,
	T_POS_CRC32,
	T_POS_CRCSTRIP,
	T_POS_MAXCHECK,
	T_POS_MAXLEN,
	T_POS_MINCHECK,
	T_POS_MINLEN,
	T_POS_RXPKTS,
	T_POS_SCRAMBLE,
	T_POS_TXPKTS,
	T_POS,
	T_RAW,
	T_REDUNDANCY_CONTROL,
	T_RX_MONITOR_MODE,
	T_RX_EQUALIZER,
	T_SAR_ENABLE,
	T_SAR_NNI,
	T_SAR_UNI,
	T_SAR_CELLS,
	T_SAR_FRAMES,
	T_SLAVE,
	T_SONET_SCRAMBLE,
	T_SFM,
	T_SFM_CLOCK,
	T_TERF_STRIP_16,
	T_TERF_STRIP_32,
	T_TERF_NOSTRIP,
	T_TR_TERF_NO_DELAY,
	T_TR_TERF_RELATIVE,
	T_TR_TERF_RX_ERROR,
	T_STEER,
	T_TIMESTAMP_HEAD,
	T_TIMESTAMP_TAIL,
	T_TX_CRC,
	T_ETH_PROMISC,
	T_ETH_10GBASESR,
	T_ETH_10GBASELR,
	T_ETH_10GBASEER,
	T_ETH_SGMII,
	T_ETH_GBIC,
	T_SAR_PATH_OAM,
	T_HLB_RANGE,
	T_SUPPRESS_ERROR,
	T_SONET,
	T_SDH,
	T_MAX,
	T_IDELAY,
	T_INFINIBAND_TAPMODE,
	T_INFINIBAND_ACTIVEMODE,
	T_INFINIBAND_MONITORMODE,
	T_INFINIBAND_FRAMER_INVERT_POLARITY,
	T_LINK_STM0,
	T_LINK_STM1,
	T_LINK_STM4,
	T_LINK_STM16,
	T_LINK_STM64,
	T_HAT_RANGE
};


#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */


#ifdef __cplusplus
}
#endif /* __cplusplus */

