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{\bf 
MYRIAS
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{\bf
Shared-Memory Parallel Architecture
}

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{\bf Architecture:}
Myrias offers the Parallel Application Management System (PAMS)
and the Scalable Parallel Supercomputer (SPS-2).
PAMS is a software environment that facilitiates the development of
applications on a shared-memory parallel architecture, and provides
run time optimization of the system during execution of several programs.
The SPS-2 is the hardware system in which PAMS is implemented.

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The SPS-2 consists of processing elements (PE's),
a Master Controller, Disk subsystems, 
and associated peripheral devices.  A
PE provides processing resource (Motorola MC68020 CPU, 68851
MMU, 68882 FPU) and memory resource (4 MBytes of SECDED DRAM).
PE's are connected hierarchically: four PE's share a single bus on a
multiple-processing element board with 16 Mbytes of memory; up to 16
multiple-processing (MP) element boards share two 33 MByte/sec backplane buses
in a card cage;  each card cage has five 11 MByte/sec
communications channels for interconnection between cages
or to the Master Controller.
MP boards can be exchanged within a cage for input/output
(I/O) boards that each connect to high-speed I/O controllers at up to
20 MBytes/sec.

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PAMS defines a virtual machine which presents
a constant interface to applications.  The virtual machine
contains a transparent control mechanism that automatically
schedules parallel tasks on PEs, enables tasks to access
data, levels loads across programs and PE's shared by a program,
and merges the results of
parallel computation.  The system uses virtual memory (32
bit) addressing,
within which each PE can address a 1024-Gbyte address space.
The hierarchically interconnected PE's
provide a transparent hierarchical memory cache for each
parallel task.  Thus, although there is no shared central
memory, each parallel task can access a large address space.

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Independent parallel tasks inherit memory images from their
parent (the task that invokes parallelism), and execute in
distinct memory spaces.  Sibling tasks do not generally affect each
others' memory spaces,
although a mechanism is provided that enables communication between them.

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{\bf Configuration:}
64 PEs and 256 MBytes minimum.
There is no known technical maximum.

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Disk controllers support striped disks that transfer at up to
20 Mbytes/sec into cache memory.
Controllers can connect to up to 4 I/O boards
that may be in the same or different cages.
Transfer rates to the I/O boards can take place at up to
20 Mbytes/sec.

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{\bf Software:}  UNIX (POSIX)

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{\bf Languages available:}
Myrias Parallel Fortran (MPF) and Myrias Parallel C (MPC)

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\begin{tabbing}
aaa\=bbb\=  \kill
Fortran characteristics:\\
\>upwards compatible with ANSI Fortran 77\\
\>single PARDO extension provides access to  parallelism\\
\>interactive source-language level debugger\\

C characteristics:\\
\>upwards compatible with proposed ANSI standard\\
\>single PARDO extension provides access to  parallelism\\
\>interactive source-language level debugger\\
\end{tabbing}

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{\bf Applications:}
General physical modelling (Monte Carlo and Particle-in-Cell
methods, computational fluid dynamics, drug design,
geophysical applications, image processing,
text retrieval, and VLSI design.

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{\bf Performance:}
Will exceed current supercomputers on an
economically significant set of applications.

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{\bf Status:}
Cost ranges from \$750K to over \$10M

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{\bf Contact:}
\begin{flushleft}
Mr. Peter A. Gregory\\
Myrias Computer Corporation\\
124 Myrtle Street\\
Boston, MA  02114\\
617-723-5727\\
\end{flushleft}

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