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{\bf
Loral MPP
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{\bf
Bit-Slice Parallel Architecture
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{\bf Architecture:}
The MPP is the product of research and development
designed to evaluate the application of a computer
architecture containing thousands of processing elements,
all operating concurrently.

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The major elements are the array unit, the array control
unit, and the staging buffer. The 128x128 processing element
has nearest neighbour connection with full-edge closure. The
16,384 processing elements, not including the extra columns
for reliability, are simple bit-serial processors, each with
a 32 element on chip shift register.

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The heart of the array unit is a custom integrated circuit
containing eight processing elements. A total of 2112 chips
have been combined with commercial memory on control chips
to give the capability to perform 400 million floating-point
operations per second.

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The array control unit contains all the logic to
provide a pipeline of commands to the array unit, an I/O
controller, and a custom-built 16-bit high-performance
microprocessor for program management. The staged buffer is
a 16-Mbyte, multidimensional I/O buffer.  This unit has the
capability necessary to reformat input date into the bit
plane format of the MPP I/O system.  The staging buffer has
an external input rate of 40 Mbytes and an internal transfer
rate to and from the array unit of 160 Mbytes in each
direction.

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{\bf Languages available:} Parallel Pascal

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{\bf Status:}
The Massively Parallel Processor was delivered to NASA
Goddard Space Flight Center in May 1983.

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{\bf Contact:}
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Loral Defense Systems Division\\
1210 Massillon Road\\
Akron, OH 44315\\
216-796-4511\\

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