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{\bf
CRAY X-MP
}



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Company no longer marketing this machine.

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{\bf
Vector Register, Parallel, Shared Memory Architecture
}



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{\bf Architecture:}
This multiprocessor pipelined vector machine has
the same architecture as the CRAY-1. The major difference is
that there are three paths from memory to the vector
registers, and the clock cycle time is 8.5 nsec on all
machines shipped after August 1986 (machines built before
August have a cycle time of 9.5 nsec.)

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\noindent
The current machines come with 1, 2, or 4 processors.
Gather/scatter hardware is available on the 2- or
4-processor version of the machine. The gather/scatter
can be chained to a load/store operation.  Users can control
all processors through calls in Fortran.  The processors
share memory.


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Other features:

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Memory up to 16 M (64-bit) words

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X-MP-2  MOS. (Bank busy time is 68 nsec and memory access time is
17 clocks.)

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X-MP-4 ECL. (Bank busy time is 34 nsec and memory
access time is 14 clocks.)

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ECL logic with .35-.5 nsec gate delay and 16 gates/chip.

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Main memory - ECL 4K RAMs with 25-nsec access time.
(Interleaving to 64 banks is possible.)

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High-speed connection at 1024 Mbytes/sec per channel (max.
2) to a CRAY SSD.  The SSD comes in various sizes up to 512
Mwords of secondary MOS memory.  Data transfer to high speed
(1200 Mbyte) DD-49 disk takes 10 Mbytes/sec.
Recent peripheral enhancements as reported under the CRAY-2.

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\noindent
{\bf Configuration:}
There are many possible front ends including IBM, CDC, VAX, and Apollo.

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{\bf Performance:} Peak of 235 Mflops per processor.

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{\bf Status:}
Cost:
\$25M to \$30M for a fully configured system at present-day
prices.

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\noindent
Delivery: Announced in August 1982, first system delivered in June 1983.

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{\bf Contact:}
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Cray Research Inc.\\
1440 Northland Drive\\
Mendota Heights, MN 55120\\
612-452-6650\\
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