Subj : Re: New Pico2
To   : Andy Burns
From : Single Stage to Orbit
Date : Mon Aug 12 2024 21:27:36

On Mon, 2024-08-12 at 19:44 +0100, Andy Burns wrote:
> 
> TNP wrote [direct via email, not the group]
> 
> > Andy Burns wrote:
> > 
> > > 2x ARM cores plus 2x RISC-V cores (perm any 2 from 4)
> > 
> > No according to what I have read. RISC or ARM. Not one of each,
> 
> Section 3.9 of the datasheet says ...
> 
> "There are two processor sockets on RP2350, referred to as core 0 and
> core 1 throughout this document. Each socket can be occupied either
> by a Cortex-M33 processor (implementing the Armv8-M Main
> architecture, plus extensions) or by a Hazard3 processor
> (implementing the RV32IMAC architecture, plus extensions)."

It also says you can have mixed cores too, one of each. That looks like
fun. 
-- 
Tactical Nuclear Kittens

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