/* -*- Mode: c -*-
 *
 *  Copyright 1993 Massachusetts Institute of Technology
 * 
 *  Permission to use, copy, modify, distribute, and sell this software and its
 *  documentation for any purpose is hereby granted without fee, provided that
 *  the above copyright notice appear in all copies and that both that
 *  copyright notice and this permission notice appear in supporting
 *  documentation, and that the name of M.I.T. not be used in advertising or
 *  publicity pertaining to distribution of the software without specific,
 *  written prior permission.  M.I.T. makes no representations about the
 *  suitability of this software for any purpose.  It is provided "as is"
 *  without express or implied warranty.
 * 
 */

#ifndef _MEASURE_H_

#define _MEASURE_H_


typedef struct 
{
  unsigned int high, low;
} MSR;

#define clearMSR(t) { t.low = 0; t.high = 0; }

#define getTSC(t)  __asm__(".byte 0x0f, 0x31" :"=a" (t.low), "=d" (t.high))
/* Puts the value of the 64-bit Time Stamp Counter into t, a MSR variable */

//#define DEBUG_PRINT

#define TRUNC_BITS 0

//#define CPS 166550000
#define CPS 200000000
#define TSCerror 17

#define DATA_READ 0x00
#define DATA_WRITE 0x01
#define DATA_READ_OR_WRITE 0x28
#define DATA_TLB_MISS 0x02
#define DATA_READ_MISS 0x03
#define DATA_WRITE_MISS 0x04
#define DATA_READ_MISS_OR_DATA_WRITE_MISS 0x29
#define WRITE_E_OR_E_STATE_LINES 0x05
#define DATA_CACHE_LINES_WRITTEN_BACK 0x06
#define INSTRUCTION_EXECUTED 0x16
#define CODE_CACHE_MISS 0x0d
#define IO_READ_OR_WRITE_CYCLE 0x1c
#define HARDWARE_INTERRUPTS 0x27
#define PIPELINE_FLUSHES 0x15
#define CODE_READ 0x0b
#define DATA_CACHE_SNOOP_HITS 0x08

#define MSR_TSC 0x10
#define MSR_CESR 0x11
#define MSR_CTR0 0x12
#define MSR_CTR1 0x13

#define CESR_COUNT_ALL_EVENTS 0x3
#define CESR_DISABLE_CTR 0x4

#define RDMSR(t, ecx)  __asm__(".byte 0x0f, 0x32" : "=a" (t.low), "=d" (t.high) : "c" (ecx))

#define WRMSR(t, ecx)  __asm__(".byte 0x0f, 0x30" : : "a" (t.low), "c" (ecx), "d" (t.high))

#define CESR_MAKE_CTRVAL(cc, es) ((cc << 6) | es)
#define CESR_MODIFY_CTR0(cesr, ctrval) \
     ((cesr & 0xffffff00) | (ctrval & 0x000000ff))
#define CESR_MODIFY_CTR1(cesr, ctrval) \
     ((cesr & 0xff00ffff) | ((ctrval & 0x000000ff)  << 16))

#define MSR_SET_CTR0(es) { MSR t; RDMSR(t, MSR_CESR); t.low = CESR_MODIFY_CTR0(t.low, CESR_MAKE_CTRVAL(CESR_COUNT_ALL_EVENTS, es)); WRMSR(t, MSR_CESR); }
#define MSR_SET_CTR1(es) { MSR t; RDMSR(t, MSR_CESR); t.low = CESR_MODIFY_CTR1(t.low, CESR_MAKE_CTRVAL(CESR_COUNT_ALL_EVENTS, es)); WRMSR(t, MSR_CESR); }
#define MSR_SET_CTR0AND1(es0, es1) { MSR t; RDMSR(t, MSR_CESR); t.low = CESR_MODIFY_CTR0(t.low, CESR_MAKE_CTRVAL(CESR_COUNT_ALL_EVENTS, es0)); t.low = CESR_MODIFY_CTR1(t.low, CESR_MAKE_CTRVAL(CESR_COUNT_ALL_EVENTS, es1)); WRMSR(t, MSR_CESR); }

extern int MSRdiff(MSR t1, MSR t2, int truncate_bits);
extern float TSCdiff_to_sec(int diff, int truncate_bits);

//#define TIME_IP
//#define TIME_OPTION
//#define TIME_TCL
//#define TIME_USER
//#define TIME_LPROT
     
#endif










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